Block Diagram
LC89971, 89971M
Control Pin Function
CONT1
Low
Low
High
High
CONT2
Low
High
Low
High
Mode (representative example)
PAL/GBI
PAL/M
—
NTSC/M
Chrominance signal delay
(CCD bits)
2 H (1834.5) + 0 H (2.5)
2 H (1822.5) + 0 H (2.5)
—
1 H (912.5) + 0 H (2.5)
Luminance signal delay
(CCD bits)
1 H (914)
1 H (908)
—
1 H (908)
Switching Voltage Levels
Low/high
Symbol
min
typ
max
Unit
Low
VL
–0.3
0.0
0.5
V
High
VH
2.0
5.0
6.0
V
Note: Since the control pin has a built-in pull-down resistor (≈ 70 kΩ), the pin will be set to the low state if left open.
FSC OUT Pin Function
This pin provides a buffer output for the clock signal input to the CLK pin.
Note: Since this pin has a built-in pull-up resistor, the pin voltage will go to the supply voltage and output will cease if left open.
No. 4900-7/9