MAQ281C Ver la hoja de datos (PDF) - Dynex Semiconductor
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MAQ281C Datasheet PDF : 55 Pages
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MAS281
No falling edge detectors are provided to prevent repeat
latching of faults held low beyond the first SYNCN high-to-low
transition. However, all FT bits are ORed together and input to
the Pl bit 1 through an edge detector to prevent the fault
register from causing multiple level 1 interrupts.
The sequence of events following a fault capture depends
on the type of fault as follows:
3.4.1 MPEN, PIOPEN, DMAPEN, PIOXEN, FLT7N, AND
SYSFN
The capture of one or more of these faults immediately sets
pending interrupt level 1 (machine error) of the Pending
Interrupt (Pl) register. Anti-repeat logic between the FT and Pl
prevents latching more than a single interrupt into the Pl before
the user interrupt service routine has cleared the FT. The
microcoded interrupt service routine reads the interrupt priority
vector from the Interrupt Unit and clears the service interrupt
from the Pl. At this point the Pl is ready to latch another
interrupt into this bit.
When this microcoded service routine acts on a level 1
interrupt, it clears the Pl bit 1, but the FT maintains the
interrupting bit(s). Therefore, a level 1 interrupt would be
latched again if there was no anti-repeat logic to prevent a
never-ending loop of interrupts.
During the SYNCN cycles between fault capture and the
beginning of the microcode interrupt handling routine, AS and
DSN are forced to their inactive states. In the case of
MPROEN, which may reflect an attempted write violation, it is
required that system hardware provide the additional
protection necessary to inhibit memory write strobe.
Interrupts are serviced at the end of the currently executing
instruction if not masked and if interrupts are enabled. System
software servicing level 1 interrupts must clear the FT via the
RCFR internal l/O command at some point in the routine to
allow subsequent faults to latch a level 1 interrupt request. A
non-destructive read of the FT is provided by the internal l/O
command RFR, but this command should be used carefully.
3.4.2 MPROEN, EXADEN, AND BUS FAULT TIME-OUT
The capture of one or more of these faults immediately sets
pending interrupt level 1 (machine error) of the Pending
Interrupt (Pl) register. Furthermore, the instruction currently
executing is aborted at the SYNCN high-to-low transition
following the SYNCN high-to-low transition that latched the
fault. The IC value saved in the interrupt linkage table for the
level 1 interrupt always points to the instruction which was in
instruction pipeline register IA at the time of the abort. Anti-
repeat logic between the FT and Pl prevents latching more
than a single interrupt into the Pl before the user interrupt
service routine has cleared the FT.
The microcoded interrupt service routine reads the
interrupt priority vector from the Interrupt Unit and clears the
serviced interrupt from the Pl. At this point the Pl is ready to
latch another interrupt into this bit. When this microcoded
service routine acts on a level 1 interrupt, it clears the Pl bit 1,
but the FT maintains the interrupting fault bit(s). Therefore, a
level 1 interrupt would be latched again if there were no anti-
repeat logic to prevent a never-ending loop of interrupts from
occurring .
3.5 DMASUPPORT
DMA data transfers are performed under the control of a
system DMA controller over the system AD bus. The user
signals that DMA requests will be honored by setting the
DMAE output high via the DMAE internal XlO command. The
DMA controller may request use of the AD bus by pulling the
module’s DMARN input low.
Unless the DMAE output is high, all such requests will be
ignored. If DMAE is high, DMARN will be acknowledged by
DMAKN dropping low. This occurs at the first SYNCN high-to-
low transition after DMARN goes low.
DMAKN low indicates that the module has relinquished
control of the AD bus by placing its AD bus, AS, DSN, M/ION,
RD/WN and IN/OPN drivers in their high impedance state.
DDN is dropped low to direct the system data bus transceivers
to drive the local AD bus and CDN is dropped low to disable
the control signal buffers. The DMA controller relinquishes
control of the AD bus by raising DMARN high. The module
responds by raising DMAKN high at the next SYNCN high-to-
low transition and continuing with program execution.
3.6 HOLD SUPPORT
The Hold state is provided to facilitate debugging of user
software by allowing the user to disable the MAS281 and
access system resources. Hold state timings is defined in
Section 6.0. The Hold state can be entered either by pulling
HOLDN low or by executing a BPT instruction with the Console
present and indicated in the Configuration Word. These two
approaches, as well as methods for using the Hold state to
single step through software, are discussed below:
3.6.1 USING HOLDN
At the completion of the currently executing instruction, the
microsequencer checks the state of the HOLDN input. If low,
the microsequencer branches to the microcode Hold service
routine. This routine decrements IC twice, enables the Hold
termination sequence, drops HLDAKN low, and enters the
Hold state. HLDAKN drops low three SYNCN cycles after the
final SYNCN cycle of the currently executing instruction. A low
on HLDAKN indicates that the module has relinquished the AD
bus by placing its AD bus, AS, DSN, M/ION, RD/WN and IN/
OPN drivers into the high impedance state and, DDN and CDN
drop low.
When HOLDN is returned high, the Hold state will end on
the subsequent high-to-low transition of SYNCN. This is
signified by raising HLDAKN, at which point thc module
resumes control of the AD bus, AS, DSN, M/ION, RD/WN and
IN/OPN signals. CDN and DDN raise high.Thc instruction
pipeline is then refilled and instruction execution resumes with
the first instruction loaded into the pipeline
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