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DS3503U

NV, I2C, Stepper Potentiometer

Maxim Integrated 

NV, I2C, Stepper Potentiometer

Table 5. Soft Power-On Reset Register Description (AAh)

BIT

NAME

6:0

—

Reserved

FUNCTION

7

SOFT POR 0: Default value.

1: Recalls values of IVR, CR, and SCR from EEPROM.

Soft Power-On Reset Register (Soft-POR)

By writing register AAh's MSB to 1, a soft power-on

reset (soft-POR) can be generated. When the MSB is

set to 1, the power-up default values of registers 00h,

01h, and 02h are recalled, and the MSB of AAh self-

clears. This soft-POR can be used to recall power-on

settings without cycling power to the DS3503.

I2C Serial Interface Description

I2C Definitions

The following terminology is commonly used to describe

I2C data transfers. (See Figure 2 and the I2C AC

Electrical Characteristics table for additional information.)

Master device: The master device controls the slave

devices on the bus. The master device generates

SCL clock pulses and START and STOP conditions.

Slave devices: Slave devices send and receive

data at the master’s request.

Bus idle or not busy: Time between STOP and

START conditions when both SDA and SCL are inac-

tive and in their logic-high states.

START condition: A START condition is generated

by the master to initiate a new data transfer with a

slave. Transitioning SDA from high to low while SCL

remains high generates a START condition.

STOP condition: A STOP condition is generated by

the master to end a data transfer with a slave.

Transitioning SDA from low to high while SCL

remains high generates a STOP condition.

Repeated START condition: The master can use a

repeated START condition at the end of one data

transfer to indicate that it will immediately initiate a

new data transfer following the current one. Repeated

STARTs are commonly used during read operations

to identify a specific memory address to begin a data

transfer. A repeated START condition is issued identi-

cally to a normal START condition.

Bit write: Transitions of SDA must occur during the

low state of SCL. The data on SDA must remain valid

and unchanged during the entire high pulse of SCL

plus the setup and hold time requirements. Data is

shifted into the device during the rising edge of the

SCL.

SDA

tBUF

tLOW

SCL

tHD:STA

tR

STOP

START

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

Figure 2. I2C Timing Diagram

tHD:DAT

tF

tHIGH

tSU:DAT

tHD:STA

tSU:STA

REPEATED

START

tSP

tSU:STO

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