M41T256Y(2007) Ver la hoja de datos (PDF) - STMicroelectronics
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M41T256Y Datasheet PDF : 30 Pages
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M41T256Y
Clock operation
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in Application
Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user
the ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the FT pin. The pin will toggle at 512Hz, when the stop bit (ST) is '0,' and the frequency
test bit (FT) is '1.'
Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
The FT pin is an open drain output which requires a pull-up resistor to VCC for proper
operation. A 500 to 10k resistor is recommended in order to control the rise time. The FT bit
is cleared on power-down.
3.8
Battery low warning
The M41T256Y automatically performs battery voltage monitoring upon power-up. The
battery low (BL) bit, bit D7 of day register, will be asserted if the battery voltage is found to
be less than approximately 2.5V. The BL bit will remain asserted until completion of battery
replacement and subsequent battery low monitoring tests, during the next power-up
sequence.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be
installed. The battery may be replaced while VCC is applied to the device.
The M41T256Y only monitors the battery when a nominal VCC is applied to the device. Thus
applications which require extensive durations in the battery back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.9
Preferred power-on/battery attach defaults
See Table 4, below.
Table 4. Preferred default values
Condition
WC
TEB(1)
TB(1)
FT
ST(1)
SLP(1)
Battery attach or initial power-up
0
X
X
0
X
X
Power-cycling (with battery)
0
UC
UC
0
UC
UC
1. X = Undetermined; UC = Unchanged
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