M2S56D20TP Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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M2S56D20TP Datasheet PDF : 36 Pages
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DDR SDRAM (Rev.0.0)
Sep.'99 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
Symbol
Parameter
tAC DQ Output Valid data delay time from CLK//CLK
tDQSCK DQ Output Valid data delay time from CLK//CLK
tCH CLK High level width
tCL CLK Low level width
CL=2.5
tCK CLK cycle time
CL=2
CL=1.5
tDH Input Setup time (DQ,DM)
tDS Input Hold time(DQ,DM)
tDIPW DQ and DM input pulse width (for each input)
tHZ Data-out-high impedance time from CLK//CLK
tLZ Data-out-low impedance time from CLK//CLK
tDQSQ DQ Valid data delay time from DQS
tDV DQ and DQS data Valid window
tDQSS Write command to first DQS latching transition
tDQSH DQS input High level width
tDQSL DQS input Low level width
tDSS DQS falling edge to CLK setup time
tDSH DQS falling edge hold time from CLK
tMRD Mode Register Set command cycle time
tWPRES Write preamble setup time
tWPST Write postamble
tWPRE Write preamble
tIS Input Setup time (address and control)
tIH Input Hold time (address and control)
tRPST Read postamble
tRPRE Read preamble
tQPST /QFC postamble during reads
tQPRE /QFC preamble during reads
tQCK /QFC output access time from CLK//CLK, for write
tQOH /QFC output hold time for writes
-75
Min. Max.
-0.75 +0.75
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5
15
10
15
12
15
0.5
0.5
1.75
-0.75 +0.75
-0.75 +0.75
-0.5 +0.5
0.35
0.75 1.25
0.35
0.35
0.2
0.2
15
0
0.4
0.6
0.25
1.1
1.1
0.4
0.6
0.9
1.1
0.4
0.6
0.9
1.1
4
1.25
2
-10
Min. Max.
-0.8 +0.8
-0.8 +0.8
0.45 0.55
0.45 0.55
8
15
10
15
12
15
0.6
0.6
2
-0.8 +0.8
-0.8 +0.8
-0.6 +0.6
0.35
0.75 1.25
0.35
0.35
0.2
0.2
15
0
0.4
0.6
0.25
1.2
1.2
0.4
0.6
0.9
1.1
0.4
0.6
0.9
1.1
4
1.25
2
Unit Notes
ns
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns 14
ns 14
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns 16
tCK 15
tCK
ns
ns
tCK
tCK
tCK
tCK
ns
ns
MITSUBISHI
ELECTRIC
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