TX4925 Ver la hoja de datos (PDF) - Toshiba

Número de pieza

componentes Descripción

Fabricante

TX4925

64-bit RISC MICROPROCESSOR

Toshiba 

INTEGRATED CIRCUIT

TOSHIBA RISC PROCESSOR

TMPR4925XB

TENTATIVE

3.3 Pin signal description

Note: In the I/O columns, “PU” indicates an I/O pin with a pull-up resistor, and the term “PD” indicates an I/O

pin with a pull-down resistor. * denotes an active-low signal when used as a suffix to a signal name.

Common Memory Interface

Signal Name

ADDR[19:0]

SADDR10

DATA[31:0]

BUSSPRT*

Type

Input/ou

tput

PU

Input/ou

tput

PU

Input/ou

tput

PU

Output

Function

A ddress

Address signals.

For SDRAM, ADDR[19:16 , 14:5] and SADDR10 are used.

When the external bus controller uses these pins, the meaning of each bit varies

with the data bus width.

The ADDR signals are also used as boot configuration signals (input) during a reset.

For details of configuration signals.

The ADDR signals are input signals only when the RESET* signal is asserted and

become output signals after the RESET* signal is deasserted.

Address10 for SDRAM.

Address single for SDRAM.

This signal is also used as a boot configuration input signal for testing. Because this

signal is used for testing, ensure that it will not pulled Low during a reset sequence.

For details of configuration signals.

This signal is used as an input signal while the RESET* signal is asserted. It

becomes an output signal once the RESET* signal has been deasserted.

Data

32-bit data bus

Bus Separate

Controls the connection and separation of devices controlled by the external bus

controller to or from a high-speed device, such as SDRAM.

H: Separate devices other than SDRAM from the data bus.

L: Connect devices other than SDRAM to the data bus.

Separation and connection are performed using external bidirectional bus buffers

(such as the 74xx245).

This signal can control either the QuickSwitch or 74xx245. These devices differ in

that the signal is also pulled Low during a write cycle with the QuickSwitch. Boot

configuration signal ADDR[19] determines w hich device is used. For details of

configuration signals.

Initial State

Input

Input

Input

High

EJC-TMPR4925XB -15

26/Dec/01 Rev 0.1

TOSHIBA CORPORATION

Share Link: