ST7261
Figure 13. Reset Timing Diagram
VDD
tDDR
OSCIN
fCPU
tOXOV
PC
RESET
FFFE FFFF
514 CPU
CLOCK
CYCLES
DELAY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+ and VIT-.
Figure 14. Reset Block Diagram
VDD
RESET
RON
200ns
Filter
tw(RSTL)out + 128 fOSC
delay
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG RESET
LVD RESET
Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
18/71