IS61LPS51218J Ver la hoja de datos (PDF) - Integrated Silicon Solution

Número de pieza

componentes Descripción

Fabricante

IS61LPS51218J

256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINED, SINGLE-CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J

WRITE CYCLE TIMING

CLK

ADSP

ADSC

ADV

Address

GW

BWE

BWx

CE

CE2

CE2

tKC

tKH

tKL

tSS

tSH

ADV must be inactive for ADSP Write tAVS

tAS

tAH

WR1

tWS

WR2

tWH

ADSP is blocked by CE inactive

ADSC initiate Write

tAVH

WR3

tCES

tWS

tWH

tWS

tWH

WR1

tCEH

tWS

tWH

WR2

CE Masks ADSP

WR3

tCES

tCES

tCEH

tCEH

CE2 and CE2 only sampled with ADSP or ADSC

OE

DATAOUT

High-Z

tDS

tDH BW4-BW1 only are applied to first cycle of WR2

DATAIN

High-Z

1a

2a

2b

2c

2d

3a

®

ISSI

Unselected with CE2

Single Write

Burst Write

Write

Unselected

18

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

PRELIMINARYINFORMATION Rev. 00B

04/29/02

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