NCV70522MN(2012) Ver la hoja de datos (PDF) - ON Semiconductor
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NCV70522MN Datasheet PDF : 29 Pages
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NCV70522MN
Table 5. DC PARAMETERS
(The DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified)
Convention: Currents Flowing in the Circuit are Defined as Positive.
Symbol
Pin(s)
Parameter
Remark/Test Conditions Min
Typ
Max Unit
SUPPLY INPUTS
VBB
Nominal Operating Supply Range
IBB
VBB Total Current Consumption
IBBS
Sleep Current in VBB (Note 7)
VDD
Logic Supply Output Voltage
ILoad
Maximum Output Current
VDD
IDDLIM
Current Limitation
ILoad_PD
Output Current in Power Down Mode
POWER ON RESET (POR) (Note 10)
Unloaded Outputs
Unloaded Outputs
6 V ≤ VBB ≤ 8 V
8 V ≤ VBB ≤ 30 V
6
30
V
12
mA
400
mA
4.5
5
5.5
V
15
mA
40
mA
150
mA
1
mA
VDDH
VDDL
VDD
VDDHYS
MOTOR DRIVER
Internal POR Comparator Threshold
Internal POR Comparator Threshold
Hysteresis Between VDDH and VDDL
VDD Rising
VDD Falling
3.6
4.2
4.5
V
3.85
V
0.10 0.35 0.60
V
IMDmax,Peak
IMDabs
Max Peak Current Through Motor Coil
TJ = 125°C
TJ = −40°C
1480
1600
mA
Absolute Error on Coil Current
TJ = 125°C
and CUR[4.0] = 15...31
−10
10
%
IMDrel
ISET_TC1
Error On Current Ratio Icoilx/Icoily
Temperature Coefficient of Coil Current
Set−Level, CUR[4:0] = 0...27
TJ ≤ 160°C
−7
−240
7
%
ppm/K
ISET_TC2
Temperature Coefficient of Coil Current
Set−Level, CUR[4:0] = 28...31
TJ ≤ 160°C
−490
ppm/K
RHS
RLS3
MOTXP
MOTXN
MOTYP
MOTYN
On−Resistance High−Side Driver,
(Note 9) CUR[4:0] = 0...31
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 23...31
RLS2
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 16...22
RLS1
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 9...15
RLS0
IMpd
DIGITAL INPUTS
On−Resistance Low−Side Driver,
(Note 9) CUR[4:0] = 0...8
Pulldown Current
VBB = 12 V, TJ = 27°C
VBB = 12 V, TJ = 160°C
VBB = 12 V, TJ = 27°C
VBB = 12 V, TJ = 160°C
VBB = 12 V, TJ = 27°C
VBB = 12 V, TJ = 160°C
VBB = 12 V, TJ = 27°C
VBB = 12 V, TJ = 160°C
VBB = 12 V, TJ = 27°C
VBB = 12 V, TJ = 160°C
HiZ Mode
0.45
W
0.94 1.25
W
0.45
W
0.94 1.25
W
0.90
W
1.9
2.5
W
1.8
W
3.8
5.0
W
3.6
W
7.5
10
W
1
mA
Ileak
DI, CLK Input Leakage (Note 8)
VIL
NXT, DIR Logic Low Threshold
CLR, CS
VIH
Logic High Threshold
TJ = 160°C
Tested @ 1 MHz input
0
frequency
2.5
0.5
mA
0.6
V
VDD
V
Rpd_CLR
CLR Internal Pulldown Resistor
120
300
kW
Rpd_TST
TST0 Internal Pulldown Resistor
3
9
kW
6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Guaranteed by
design.
7. Current with all analogue cells in power down. Logic is powered but no clocks running. All outputs unloaded, no inputs floating.
8. Not valid for pins with internal Pulldown resistor
9. Characterization Data Only
10. POR is derived from VDD. For proper POR operation VBB needs to be minimal VBB_min.
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