MPC9600AE Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
Fabricante
MPC9600AE Datasheet PDF : 15 Pages
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MPC9600 Data Sheet
PCLK
PCLK
FB_IN
VPP
t()
VCMR
VCC
VCC 2
GND
Figure 14. Propagation Delay (tØ, status phase offset)
Test Reference
VCC
VCC 2
GND
tP
T0
DC = tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
Figure 16. Output Duty Cycle (DC)
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
TCLK
FB_IN
t()
VCC
VCC 2
GND
VCC
VCC 2
GND
Figure 15. Propagation Delay (tØ) Test Reference
tSK(O)
VCC
VCC 2
GND
VCC
VCC 2
GND
The pin-to-pin skew is defined as the worst case difference in propagation delay
between any similar delay path within a single device
Figure 17. Output-to-Output Skew tSK(O)
TN
TN+1
TJIT(CC) = |TN–TN+1|
The variation in cycle time of a signal between adjacent cycles, over a random
sample of adjacent cycle pairs
Figure 18. Cycle-to-Cycle Jitter
CCLK
(PCLK)
FB_IN
TJIT() = |T0–T1mean|
The deviation in T0 for a controlled edge with respect to a T0
mean in a random sample of cycles
Figure 20. I/O Jitter
TJIT(P) = |TN–1/f0|
T0
The deviation in cycle time of a signal with respect to the ideal period
over a random sample of cycles
Figure 19. Period Jitter
VCC = 3.3 V
2.4
VCC = 2.5 V
1.8
0.55
0.6
tF
tR
Figure 21. Transition Time Test Reference
MPC9600 REVISION 6 JANUARY 7, 2013
12
©2013 Integrated Device Technology, Inc.
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