30833FJGP Ver la hoja de datos (PDF) - Renesas Electronics
Número de pieza
componentes Descripción
Fabricante
30833FJGP Datasheet PDF : 527 Pages
| |||
10. Interrupts___________________________________ 89
10.1 Types of Interrupts ................................................................................................. 89
10.2 Software Interrupts ................................................................................................ 89
10.2.1 Undefined Instruction Interrupt ..................................................................... 89
10.2.2 Overflow Interrupt ........................................................................................... 89
10.2.3 BRK Interrupt .................................................................................................. 89
10.2.4 BRK2 Interrupt ................................................................................................ 90
10.2.5 INT Instruction Interrupt ................................................................................. 90
10.3 Hardware Interrupts ............................................................................................... 90
10.3.1 Special Interrupts ............................................................................................ 90
10.3.2 Peripheral Function Interrupt ........................................................................ 91
10.4 High-Speed Interrupt ............................................................................................. 91
10.5 Interrupts and Interrupt Vectors ........................................................................... 91
10.5.1 Fixed Vector Tables ........................................................................................ 92
10.5.2 Relocatable Vector Tables .............................................................................. 92
10.6 Interrupt Request Reception ................................................................................. 95
10.6.1 I Flag and IPL ................................................................................................... 95
10.6.2 Interrupt Control Register and RLVL Register ............................................. 95
10.6.3 Interrupt Sequence ......................................................................................... 99
10.6.4 Interrupt Response Time .............................................................................. 100
10.6.5 IPL Change when Interrupt Request is Acknowledged ............................. 101
10.6.6 Saving a Register .......................................................................................... 102
10.6.7 Restoration from Interrupt Routine ............................................................. 102
10.6.8 Interrupt Priority ............................................................................................ 103
10.6.9 Interrupt Priority Level Select Circuit ......................................................... 103
______
10.7 INT Interrupt .......................................................................................................... 105
______
10.8 NMI Interrupt ......................................................................................................... 106
10.9 Key Input Interrupt ............................................................................................... 106
10.10 Address Match Interrupt .................................................................................... 107
10.11 Intelligent I/O Interrupt and CAN Interrupt ....................................................... 108
11. Watchdog Timer ____________________________ 111
12. DMAC_____________________________________ 114
12.1 Transfer Cycles .................................................................................................... 121
12.1.1 Effect of Source and Destination Addresses ............................................. 121
12.1.2 Effect of the DS Register .............................................................................. 121
12.1.3 Effect of Software Wait State ....................................................................... 121
________
12.1.4 Effect of RDY Signal ..................................................................................... 121
A-3
Share Link: 