CY7C4265A Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C4265A

8K/16K x 18 Deep Sync FIFOs

Cypress Semiconductor 

CY7C4255, CY7C4265, CY7C4265A

Switching Waveforms (continued)

Figure 5. Reset Timing[17]

RS

REN, WEN,

LD

EF,PAE

FF,PAF,

HF

Q0–Q17

tRS

tRSR

tRSF

tRSF

tRSF

[18]

OE = 1

OE = 0

Figure 6. First Data Word Latency after Reset with Simultaneous Read and Write

WCLK

tDS

D0 –D17

D0 (FIRSTVALID WRITE)

D1

D2

WEN

tENS

RCLK

[19]

tFRL

tSKEW2

tREF

EF

D3

D4

REN

Q0 –Q17

OE

tOLZ

tA

tOE

[20]

tA

D0

D1

Notes

17. The clocks (RCLK, WCLK) can be free-running during reset.

18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.

19. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or

tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).

20. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06004 Rev. *E

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