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ADCMP567BCP

Dual Ultrafast Voltage Comparator

Analog Devices 

ADCMP567

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND 1

–INA 2

+INA 3

VCC 4

VCC 5

+INB 6

–INB 7

GND 8

PIN 1

INDICATOR

ADCMP567

TOP VIEW

(Not to Scale)

24 VEE

23 NC

22 VEE

21 VCC

20 VCC

19 VEE

18 NC

17 VEE

NC = NO CONNECT

03632-0-002

Figure 2. ADCMP567 Pin Configuration

Table 3. ADCMP567 Pin Descriptions

Pin No.

Mnemonic

Function

1

GND

Analog Ground

2

−INA

Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven

in conjunction with the noninverting A input.

3

+INA

Noninverting analog input of the differential input stage for Channel A. The noninverting A input must

be driven in conjunction with the inverting A input.

4

VCC

Positive Supply Terminal

5

VCC

Positive Supply Terminal

6

+INB

Noninverting analog input of the differential input stage for Channel B. The noninverting B input must

be driven in conjunction with the inverting B input.

7

−INB

Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven

in conjunction with the noninverting B input.

8

GND

Analog Ground

9

GND

Analog Ground

10

LEB

One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the

output will track changes at the input of the comparator. In the latch mode (logic high), the output will

reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven

in conjunction with LEB.

11

LEB

One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the

output will track changes at the input of the comparator. In the latch mode (logic low), the output will

reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven

in conjunction with LEB.

12

NC

No Connect. Leave pin unconnected.

13

VDD

Logic Supply Terminal

14

QB

One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the

noninverting input is greater than the analog voltage at the inverting input (provided the comparator is

in the compare mode). See the LEB description (Pin 11) for more information.

15

QB

One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the

noninverting input is greater than the analog voltage at the inverting input (provided the comparator is

in the compare mode). See the LEB description (Pin 11) for more information.

16

VDD

Logic Supply Terminal

17

VEE

Negative Supply Terminal

18

NC

No Connect. Leave pin unconnected.

19

VEE

Negative Supply Terminal

20

VCC

Positive Supply Terminal

21

VCC

Positive Supply Terminal

Rev. 0 | Page 6 of 16

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