AT91SAM7SE256(2008) Ver la hoja de datos (PDF) - Atmel Corporation

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componentes Descripción

Fabricante

AT91SAM7SE256
(Rev.:2008)

Product Description

Atmel Corporation 

7.8 Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Eleven channels

– Two for each USART

– Two for the Debug Unit

– Two for the Serial Synchronous Controller

– Two for the Serial Peripheral Interface

– One for the Analog-to-digital Converter

• Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirements

• Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):

Receive

Receive

Receive

Receive

Receive

Receive

Transmit

Transmit

Transmit

Transmit

Transmit

DBGU

USART0

USART1

SSC

ADC

SPI

DBGU

USART0

USART1

SSC

SPI

20 AT91SAM7SE512/256/32 Preliminary

6222ES–ATARM–04-Jan-08

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