AT91SAM7SE32(2008) Ver la hoja de datos (PDF) - Atmel Corporation

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AT91SAM7SE32
(Rev.:2008)

Product Description

Atmel Corporation 

AT91SAM7SE512/256/32 Preliminary Summary

7. Processor and Architecture

7.1 ARM7TDMI Processor

• RISC processor based on ARMv4T Von Neumann architecture

– Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)

• Two instruction sets

– ARM® high-performance 32-bit instruction set

– Thumb® high code density 16-bit instruction set

• Three-stage pipeline architecture

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

7.2 Debug and Test Features

• EmbeddedICE™ (Integrated embedded in-circuit emulator)

– Two watchpoint units

– Test access port accessible through a JTAG protocol

– Debug communication channel

• Debug Unit

– Two-pin UART

– Debug communication channel interrupt handling

– Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on all digital pins

7.3 Memory Controller

• Programmable Bus Arbiter

– Handles requests from the ARM7TDMI and the Peripheral DMA Controller

• Address decoder provides selection signals for

– Four internal 1 Mbyte memory areas

– One 256-Mbyte embedded peripheral area

– Eight external 256-Mbyte memory areas

• Abort Status Registers

– Source, Type and all parameters of the access leading to an abort are saved

– Facilitates debug by detection of bad pointers

• Misalignment Detector

– Alignment checking of all data accesses

– Abort generation in case of misalignment

• Remap Command

– Remaps the SRAM in place of the embedded non-volatile memory

– Allows handling of dynamic exception vectors

• 16-area Memory Protection Unit (Internal Memory and peripheral protection only)

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6222ES–ATARM–04-Jan-08

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