IRS2117 Ver la hoja de datos (PDF) - Infineon Technologies
Número de pieza
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Fabricante
IRS2117 Datasheet PDF : 26 Pages
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The IRS21171SPBF is not recommended for new designs. For new designs, we recommend IRS2117SPbF or IRS25752LPbF
IRS211(7,71,8)(S)
DC+ BUS
DC+ BUS
Q1
OFF
VS
D1
IL
Q2
D2
OFF
Q1
OFF
VS
Q2
ON
D1
IL
DC- BUS
Figure 8: D1 conducting
DC- BUS
Figure 9: Q2 conducting
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus,
rather it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS
transient”.
The circuit shown in Figure 10 depicts a half bridge circuit with parasitic elements shown; Figures 11 and 12
show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances
in the power circuit from the die bonding to the PCB tracks are lumped together in LD and LS for each switch.
When the high-side switch is on, VS is below the DC+ voltage by the voltage drops associated with the power
switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current can
momentarily flow in the low-side freewheeling diode due to the inductive load connected to VS (the load is not
shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC)
to the load and a negative voltage between VS and the DC- Bus is induced (i.e., the COM pin of the HVIC is at
a higher potential than the VS pin).
DC+ BUS
Q1
D1
OFF
Figure 10: Parasitic Elements
Figure 11: VS positive
VS +
_ VLD2
IL
Q2
D2
OFF
+
VLS2
_
DC- BUS
Figure 12: VS negative
In a typical power circuit, dV/dt is typically designed to be in the range of 1-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt
is greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding
applications. An indication of the IRS211(7,71,8)’s robustness can be seen in Figure 13, where there is
represented the IRS211(7,71,8) Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A
negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage;
viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs
transients fall inside SOA.
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© 2008 International Rectifier
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