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LH28F400SU-LC

4M (512K × 8, 256K × 16) Flash Memory

Sharp Electronics 

4M (512K × 8, 256K × 16) Flash Memory

LH28F400SU-LC

Timing Nomenclature

For 3.3 V systems use 1.5 V cross point definitions.

Each timing parameter consists of 5 characters. Some common examples are defined below:

tCE tELQV time (t) from CE » (E) going low (L) to the outputs (Q) becoming valid (V)

tOE tGLQV time (t) from OE » (G) going low (L) to the outputs (Q) becoming valid (V)

tACC tAVQV time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)

tAS tAVWH time (t) from address (A) valid (V) to WE » (W) going high (H)

tDH tWHDX time (t) from WE » (W) going high (H) to when the data (D) can become undefined (X)

PIN CHARACTERS

A Address Inputs

D Data Inputs

Q Data Outputs

E CE » (Chip Enable)

G OE» (Output Enable)

W WE (Write Enable)

P RP » (Deep Power-Down Pin)

R RY »/BY » (Ready/Busy)

V Any Voltage Level

3 V VCC at 3.0 V Min.

PIN STATES

H High

L Low

V Valid

X Driven, but not necessarily valid

Z High Impedance

3.0

INPUT 1.5

0.0

TEST POINTS

1.5 OUTPUT

NOTE:

AC test inputs are driven at 3.0 V for a Logic '1'

and 0.0 V for a Logic '0'. Input timing begins,

and output timing ends at 1.5 V. Input rise

and fall times (10% to 90%) < 10 ns.

28F400SUH-LC15-14

Figure 16. Transient Input/Output

Reference Waveform (VCC = 3.3 V)

2.5 ns OF 50 Ω TRANSMISSION LINE

FROM OUTPUT

UNDER TEST

TEST

POINT

TOTAL CAPACITANCE = 50 pF

28F400SUH-LC15-15

Figure 17. Transient Equivalent Testing

Load Circuit (VCC = 3.3 V)

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