ISL1221 Ver la hoja de datos (PDF) - Renesas Electronics
Número de pieza
componentes Descripción
Fabricante
ISL1221 Datasheet PDF : 24 Pages
| |||
ISL1221
Event Detect Timing Diagram with
Sampling Mode Enabled
Case 1, Switch Opened Before Ipu
Ipu
ON
OFF
15 CLKS (8x)
EXT. OPEN
SWITCH
CLOSED
HIGH
EVIN
LOW
HIGH
EVDET
LOW
8 CLKS (8x)
Case 2, Switch Opened After Ipu
Ipu
ON
OFF
15 CLKS (8x)
EXT. OPEN
SWITCH
CLOSED
HIGH
EVIN
LOW
HIGH
EVDET
LOW
8 CLKS (8x)
Case 3, Switch Bounced
Ipu
ON
OFF
15 CLKS (8x)
EXT. OPEN
SWITCH
CLOSED
HIGH
EVIN
LOW
HIGH
EVDET
LOW
8 CLKS (8x)
The ISL1221 can operate independently or in conjunction with
a microcontroller for low power operation modes or in battery
backup modes.
The event detection and time stamp circuits operate in either
main VDD power or battery backup mode.
Users have the option to connect EVIN (see EVINEB bit) to an
internal pull-up current source that operates at 1µA (always on
mode), which can drop to 400nA in battery backup mode. User
selectable event sampling modes are also available which will
effectively reduce power consumption with 1/4-Hz, 1-Hz and 2-Hz
sample detection rates. The EVIN input is pulsed ON/OFF when
in sampling mode for power savings advantages (see Table 1, 2,
3, and 4).
The EVIN also has a user selectable time based hysteresis
filter (see EHYS bits) to implement switch de-bouncing during
an event detection. The EVIN signal must be high for the
duration of the selected time period. The time periods available
are 0 times delay (no time based hysteresis) to 3.9ms,
15.625ms or 31.25ms (see Table 1, 2, 3, and 4).
TABLE 1. IDD (VDD = 3V, tHYS = 3.9ms)
fSMP
1/4Hz
DELTA IDD
20.5nA
1Hz
82nA
2Hz
164nA
TABLE 2. IDD (VDD = 5.0V, tHYS = 3.9ms)
fSMP
1/4Hz
DELTA IDD
65.8nA
1Hz
263.3nA
2Hz
526.5nA
TABLE 3. IDD (VDD = 3.0V, tHYS = 15.625ms)
fSMP
1/4Hz
DELTA IDD
82nA
1Hz
328nA
2Hz
656.3nA
TABLE 4. IDD (VDD = 5.0V, tHYS = 15.625ms)
fSMP
1/4Hz
DELTA IDD
264nA
1Hz
1.05µA
2Hz
2.1µA
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation of
second, minute, hour, day of week, date, month, and year. The
RTC also has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that controls
24 hour or AM/PM format. When the ISL1221 powers up after
the loss of both VDD and VBAT, the clock will not begin
incrementing until at least one byte is written to the clock
register.
FN6316 Rev 1.00
July 15, 2010
Page 10 of 24
Share Link: 