ISL12023 Ver la hoja de datos (PDF) - Renesas Electronics

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Fabricante

ISL12023

Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving

Renesas Electronics 

ISL12023

Package Outline Drawing

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09

A

13

5.00 ±0.10

14

8

6.40

4.40 ±0.10

2

3

PIN #1

I.D. MARK

SEE

DETAIL "X"

0.20 C B A

1

7

0.65

B

TOP VIEW

H

C

SEATING

PLANE

0.10 C

0.05

1.20 MAX

0.25 +0.05/-0.06 5

0.10 CBA

SIDE VIEW

0.09-0.20

END VIEW

1.00 REF

0.90 +0.15/-0.10

0.05 MIN

0.15 MAX

DETAIL "X"

GAUGE

PLANE

0.25

0°-8°

0.60 ±0.15

(1.45)

(5.65)

(0.65 TYP)

(0.35 TYP)

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.80mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead is 0.07mm.

6. Dimension in ( ) are for reference only.

7. Conforms to JEDEC MO-153, variation AB-1.

FN6682 Rev 3.00

December 6, 2011

Page 29 of 29

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