A3977(2013) Ver la hoja de datos (PDF) - Allegro MicroSystems

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A3977
(Rev.:2013)

Microstepping DMOS Driver with Translator

Allegro MicroSystems 

A3977

Microstepping DMOS Driver with Translator

Functional Description (cont’d)

Fixed Off-Time. The internal PWM current-control

circuitry uses a one shot to control the time the drivers

remain off. The one shot off-time, toff, is determined by

the selection of an external resistor (RT) and capacitor (CT)

connected from the RC timing terminal to ground. The off-

time, over a range of values of CT = 470 pF to 1500 pF and

RT = 12 kΩ to 100 kΩ is approximated by:

toff = RTCT

RC Blanking. In addition to the fixed off-time of the

PWM control circuit, the CT component sets the compara-

tor blanking time. This function blanks the output of the

current-sense comparator when the outputs are switched by

the internal current-control circuitry. The comparator out-

put is blanked to prevent false over-current detection due

to reverse recovery currents of the clamp diodes, and/or

switching transients related to the capacitance of the load.

The blank time tBLANK can be approximated by:

tBLANK = 1400CT

Charge Pump. (CP1 and CP2). The charge pump is

used to generate a gate supply greater than VBB to drive

the source-side DMOS gates. A 0.22 μF ceramic capacitor

should be connected between CP1 and CP2 for pumping

purposes. A 0.22 μF ceramic capacitor is required between

VCP and VBB to act as a reservoir to operate the high-side

DMOS devices.

VREG. This internally generated voltage is used to operate

the sink-side DMOS outputs. The VREG terminal should

be decoupled with a 0.22 μF capacitor to ground. VREG is

internally monitored and in the case of a fault condition,

the outputs of the device are disabled.

Enable Input (ENABLE). This active-low input enables

all of the DMOS outputs. When logic high the outputs are

disabled. Inputs to the translator (STEP, DIRECTION,

MS1, MS2) are all active independent of the ENABLE

input state.

Shutdown. In the event of a fault (excessive junction

temperature, or low voltage on VCP) the outputs of the

device are disabled until the fault condition is removed. At

power up, and in the event of low VDD, the undervoltage

lockout (UVLO) circuit disables the drivers and resets the

translator to the HOME state.

Sleep Mode (SLEEP). An active-low control input used

to minimize power consumption when not in use. This

disables much of the internal circuitry including the output

DMOS, regulator, and charge pump. A logic high allows

normal operation and startup of the device in the home

position. When coming out of sleep mode, wait

1 ms before issuing a STEP command to allow the charge

pump (gate drive) to stabilize.

Percent Fast Decay Input (PFD). When a STEP input

signal commands a lower output current from the previous

step, it switches the output current decay to either slow-,

fast-, or mixed-decay depending on the voltage level at the

PFD input. If the voltage at the PFD input is greater than

0.6 VDD then slow-decay mode is selected. If the voltage

on the PFD input is less than 0.21 VDD then fast-decay

mode is selected. Mixed decay is between these two levels.

This terminal should be decoupled with a 0.1 μF capacitor.

Mixed Decay Operation. If the voltage on the PFD in-

put is between 0.6VDD and 0.21VDD, the bridge will oper-

ate in mixed-decay mode depending on the step sequence

(see figures). As the trip point is reached, the device will

go into fast-decay mode until the voltage on the RC termi-

nal decays to the voltage applied to the PFD terminal. The

time that the device operates in fast decay is approximated

by:

tFD = RTCTIn (0.6VDD/VPFD)

After this fast decay portion, tFD, the device will

switch to slow-decay mode for the remainder of the fixed

off-time period.

Allegro MicroSystems, LLC

8

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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