23C256 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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Fabricante

23C256

NAND INTERFACE 256M-BIT MASK-PROGRAMMABLE ROM

NEC => Renesas Technology 

Read Cycle Timing Chart (3)

(In case of read mode (3))

CLE

tCLS

/CE

tCS

/WE

ALE

tCLH

tCH

tCS

tWC

tALH

tALS tWP tWH

tR

tALH

tAR2

tRR

tRC

tRC

tCEH

tCRY

tCHZ

/RE

I/O0 to I/O7

tDS tDH

50H

R, /B

tWB

tDS

tDS

tDS

A0 to A3 A9 to A16 A17 to A24

High-Z

tDH

tDH

tDH

tRP tREH

tRHZ

DOUT

512+N

tREA

DOUT

512+N+1

tRHZ

High-Z

DOUT

527

tRB

Access

page M

Output page M data

Remarks 1. Start address (SA) specification when read is performed with command 50H. N: 0 to 15

2. The start address of area C (redundancy data) is specified with A0 to A3 during the 1st address cycle. At this time, A4 to A7 are Don't Care.

3. The time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R, /B output pin.

4. The data that is output is FFH.

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