HV300LG-G Ver la hoja de datos (PDF) - Supertex Inc

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componentes Descripción

Fabricante

HV300LG-G

Hotswap, Inrush Current Limiter Controllers (Negative Supply Rail)

Supertex Inc 

HV300

From the second equation for an over voltage set point of

65V, the value of R3 may be calculated.

OVOFF = 1.26 = 65 • R3 / 500kΩ

R3 = (1.26 • 500K) / 65 = 9.69 kΩ

Undervoltage/Overvoltage Operation

GND

UVOFF

UVON

VIN

The closest 1% value is 9.76kΩ.

From the first equation for an under voltage set point of 35V,

the value R2 can be calculated.

OVON

OVOFF

Pass

Transistor ON

UVOFF = 1.16 = 35 • (R2 + R3) / 500K

R2 = (1.16 • 500K) / 35 – 9.76kΩ = 6.81kΩ.

The closest 1% value is 6.81kΩ.

Then R1 = 500K – (R2 + R3) = 483kΩ

The closest 1% value is 487kΩ.

OFF

Current Limit

The current limit magnitude above which the current will

not be allowed to rise during startup is programmed using a

sense resistor connected from the SENSE pin to VEE pin.

For example to program a current limit of 1.0A, one would

choose a resistor as follows:

RSENSE = 50mV / ISENSE

RSENSE = 50mV / 1.0A

RSENSE = 50mΩ

Pin Description

Pin #

1

2

3

4

Function

PWRGD

OV

UV

VEE

Description

This pin is held low during inrush current limiting and changes to high impedance state when the

external MOSFET is fully turned on. This pin may be used as an enable control when connected

directly to a PWM power module.

This pin, when raised above its high threshold, will immediately cause the GATE pin to be pulled

low. The GATE pin will remain low until the voltage on this pin falls below the low threshold limit,

initiating a new start-up cycle.

This Under Voltage sense pin, when below its low threshold limit will ensure that the GATE pin

is low. The GATE pin will remain low until the voltage on this pin rises above the high threshold,

initializing a new start-up cycle.

This pin is the negative voltage power supply input to the circuit.

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VDD This pin is the positive voltage power supply input to the circuit.

This pin provides a current output so that a timing ramp voltage is generated when a capacitor is

connected. The initial portion of the ramp provides a time delay, which in conjunction with the Un-

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RAMP der Voltage detection circuit eliminates circuit card insertion contact bounce. The RAMP pin also

controls the delay between the current limit mode disengaging and the PWRGD signal activating;

as well as the current rise profile after the initial turn on delay.

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GATE This is the GATE driver output for the external N-Channel MOSFET.

8

SENSE

The current sense resistor connected from this pin to VEE pin programs the current limit. Constant

current output mode is established when the voltage drop across this resistor reaches 50mV.

● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

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