AAT1106ICB-0.6-T1 Ver la hoja de datos (PDF) - Skyworks Solutions
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AAT1106ICB-0.6-T1 Datasheet PDF : 19 Pages
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Input Capacitor Selection
The input capacitor reduces the surge current drawn
from the input and switching noise from the device. The
input capacitor impedance at the switching frequency
shall be less than the input source impedance to prevent
high frequency switching current passing to the input. A
low ESR input capacitor sized for maximum RMS current
must be used. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of their low
ESR and small temperature coefficients. A 4.7μF ceram-
ic capacitor is sufficient for most applications.
To estimate the required input capacitor size, determine
the acceptable input ripple level (VPP) and solve for C.
The calculated value varies with input voltage and is a
maximum when VIN is double the output voltage.
VO
VIN
·
⎛⎝1 -
VO ⎞
VIN ⎠
CIN =
⎛ VPP
⎝ IO
- ESR⎞⎠ · FS
VO
VIN
·
⎛⎝1 -
VO ⎞
VIN ⎠
=
1
4
for
VIN
=
2
·
VO
1
CIN(MIN) = ⎛ VPP
⎝ IO
- ESR⎞⎠ · 4 · FS
Always examine the ceramic capacitor DC voltage coeffi-
cient characteristics when selecting the proper value. For
example, the capacitance of a 10μF, 6.3V, X5R ceramic
capacitor with 5.0V DC applied is actually about 6μF.
The maximum input capacitor RMS current is:
IRMS = IO ·
VO
VIN
·
⎛⎝1 -
VO ⎞
VIN ⎠
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current:
VO
VIN
· ⎛⎝1 -
VO ⎞
VIN ⎠
=
D · (1 - D) =
0.52 = 1
2
for VIN = 2 · VO.
DATA SHEET
AAT1106
600mA Step-Down Converter
I = RMS(MAX)
IO
2
The term
VO
VIN
·
⎛⎝1 -
VO ⎞
VIN ⎠
appears in both the input voltage
ripple and input capacitor RMS current equations and is
at maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle. The input capacitor
provides a low impedance loop for the edges of pulsed
current drawn by the AAT1106. Low ESR/ESL X7R and
X5R ceramic capacitors are ideal for this function. To
minimize stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps the
high frequency content of the input current localized,
minimizing EMI and input voltage ripple. The proper
placement of the input capacitor (C1) can be seen in the
evaluation board layout in Figure 2. A laboratory test set-
up typically consists of two long wires running from the
bench power supply to the evaluation board input voltage
pins. The inductance of these wires, along with the low-
ESR ceramic input capacitor, can create a high Q network
that may affect converter performance. This problem
often becomes apparent in the form of excessive ringing
in the output voltage during load transients. Errors in the
loop phase and gain measurements can also result. Since
the inductance of a short PCB trace feeding the input
voltage is significantly lower than the power leads from
the bench power supply, most applications do not exhib-
it this problem. In applications where the input power
source lead inductance cannot be reduced to a level that
does not affect the converter performance, a high ESR
tantalum or aluminum electrolytic should be placed in
parallel with the low ESR, ESL bypass ceramic. This
dampens the high Q network and stabilizes the system.
Output Capacitor Selection
The output capacitor is required to keep the output volt-
age ripple small and to ensure regulation loop stability.
The output capacitor must have low impedance at the
switching frequency. Ceramic capacitors with X5R or
X7R dielectrics are recommended due to their low ESR
and high ripple current. The output ripple VOUT is deter-
mined by:
ΔVOUT ≤
VOUT ·
VIN
(VIN -
· fOSC
VOUT)
·L
·
⎛⎝ESR
+
8
·
1
fOSC
·
⎞
C3⎠
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 4.7μF to
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201970B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 15, 2013
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