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Fabricante

PM8313D3MX

M13 MULTIPLEXER

PMC-Sierra 

DATA SHEET

PMC-920702

ISSUE 5

PM8313 D3MX

M13 MULTIPLEXER

DESCRIPTION

The PM8313 D3MX M13 Multiplexer supports asynchronous multiplexing and

demultiplexing of 28 DS1s, 21 E1s or 7 DS2s into a DS3 signal. The device

supports ANSI T1.107, Bell Communications Research TR-TSY-000009 and

CCITT Recommendation G.747 standards.

Receive DS3 framing is provided by the DS3 FRMR Framer Block. The FRMR

accepts either a B3ZS encoded bipolar, or a unipolar signal compatible with M23

and C-bit parity applications. The FRMR frames to a DS3 signal with a maximum

average reframe time of 1.5 ms in the presence of a 10-3 bit error rate. The

FRMR indicates line code violations, loss of signal, framing bit errors, parity

errors, C-bit parity errors, and far end block errors (FEBE). The FRMR detects

far end receive failure (X-bits set to 0), the alarm indication signal (AIS), and the

idle signal. The FRMR is an off-line framer, indicating both out of frame (OOF)

and change of frame alignment (COFA) events. The error events (FER, CBIT

PARITY ERROR, FEBE, etc.) are still indicated while the framer is OOF, based

on the previous frame alignment.

The C-bit parity far end alarm channel (FEAC) and path maintenance data link

are supported. Bit oriented codes in the FEAC channel are detected by the

RBOC Bit-Oriented Code Receiver Block. If enabled, the RBOC generates an

interrupt when a valid code has been received. The path maintenance data link is

terminated using either the RFDL Data Link Receiver Block or an external HDLC

receiver. The RFDL supports polled, interrupt driven, and DMA servicing.

DS3 error event accumulation is provided by the DS3 PMON Performance

Monitor Block. The PMON accumulates framing bit errors, line code violations,

excessive zeros occurrences, parity errors, C-bit parity errors, and far end block

errors. Error accumulation continues even while the off-line framer is indicating

OOF. The counters are intended to be polled once per second, and are sized so

as not to saturate at a 10-3 bit error rate. Transfer of count values to holding

registers is initiated through the microprocessor interface.

DS3 transmit framing insertion is provided by the DS3 TRAN Transmitter Block. It

outputs either a B3ZS encoded bipolar signal, or a unipolar signal. The DS3

TRAN inserts the X, P, M, C, and F bits into the outgoing DS3 stream. The DS3

TRAN block inserts far end receive failure, AIS, and the idle signal under the

control of external inputs, or internal register bits. Diagnostic features are

provided to allow the generation of line code violation error events, parity error

events, framing bit error events, and when enabled for the C-bit parity

application, C-bit parity error events, and far end block error events. External

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