QL82SD-7PT280C Ver la hoja de datos (PDF) - QuickLogic Corporation
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QL82SD-7PT280C Datasheet PDF : 60 Pages
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QL82SD Device Data Sheet Rev C
SERDES Switching Characteristics - Deserializer/Receiver
Table 17: Deserializer / Receiver Switch Characteristics
CDR (10:1) Mode
Symbol
Parameter
Conditions
Min
Typ
tRCP
tRDC
tDD
tRXPD
tDSR1
ChX_rxclk Period
ChX_rxclk Duty Cycle
Deserializer Delay
ChX_rxclk to ChX_rxd[9..0]
Deserializer PLL Lock Time
from powered-down state
28.5
Figure 23
45
2 × tRCP + 1.5
1.5
Figure 24: 25 MHz
Figure 24: 50 MHz
T
50
2 × tRCP + 2.5
2.5
5
8
tDSR2
tDJIT
Figure : 25 MHz
Deserializer PLL Lock Time from SYNCPAT
Figure : 50 MHz
Pad_ChX_p/n Jitter
25 MHz
50 MHz
1
0.75
±350
±200
Channel Link (8:1, 7:1, 4:1) Mode
Symbol
Parameter
Conditions
Min
Typ
Max
40.0
55
2 × tRCP + 3.5
3.5
Max
Units
nS
%
nS
nS
uS
uS
uS
uS
pS
pS
Units
tRCP
ChX_rxclk Period
Mode Dependent
LVDS Link -1
Frequency
Compression
Mode
Mode Dependent
LVDS Link -1
T
Frequency
nS
Compression
Mode
tRDC
tDD
ChX_rxclk Duty Cycle
Deserializer Delay
45
50
55
%
2 × tRCP + 1.5 2 × tRCP + 2.5 2 × tRCP + 3.5
nS
tRXPD
ChX_rxclk to ChX_rxd[N-1..0]
1.5
2.5
3.5
nS
tRXDS
tRXDH
Pad_ChX_p/n Setup to Strobe Position
Pad_ChX_p/n Hold to Strobe Position
Figure 26
150
200
pS
150
200
pS
tSCD
Pad_ClkX_p/n to Serial Clock Delay a
0.6
0.8
1
nS
tSCP
tRXD[N-1]
Serial Clock Period
Receiver Input Strobe Position for Bit [N-1]
[N-1] × tSCP + 1.1
T/mode
nS
[N-1] × tSCP + 2.4 nS
tDSR1
Deserializer PLL Lock Time from
powered-down state
Figure 24: 25 MHz
Figure 24: 50 MHz
5
8
uS
uS
tDJIT
Pad_ChX_p/n Jitter
25 MHz
50 MHz
±300
pS
±150
pS
Asynchronous Level Conversion (1:1) Mode
tADD
Asynchronous Deserializer Delay -
Data Channel
1.7
nS
Figure 27
tADC
AsynchrCohnaonunseSl eCrlioaclizkear Delay -
0.6
0.8
1
nS
a. These values include the delay resulting from application of internal compensation for data/clock skew.
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Preliminary
© 2002 QuickLogic Corporation
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