SC1480A Ver la hoja de datos (PDF) - Semtech Corporation
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SC1480A Datasheet PDF : 23 Pages
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SC1480A
POWER MANAGEMENT
Application Information (Cont.)
Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All
components that are referenced to VSSA should connect to it locally at the chip. VSSA should connect to power
ground at the output capacitor(s) only.
.eedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.
Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run them in
a quiet layer if possible.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and
connected directly to them on the same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
minimum land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOS.ETs to reduce parasitic impedances (and MOS.ET switching losses), the low-side MOS.ET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC1480A DDR2 reference design used in the Design Procedure section while explaining the
layout guidelines in more detail.
VDDQ VBAT
5VSUS
5VRUN
VBAT
R1
10k0
0402
REFOUT
VTT
PGOOD
C7
0u1
0402
R6
10k0
0402
R2
715k
0402
C8
1n
0402
C2
1u
0402
R7
10R
0402
R3
470k
0402
R4
10R
0402
C9
1u
0603
U1
1 REFIN
2 TON
3 REFOUT
4 VCCA
5 FB
6 PGD
7 VSSA
SC1480A
BST 14
DH 13
LX 12
ILIM 11
VDDP 10
DL 9
PGND 8
SOD323
D1
Q1 5 6
FDS6982S
C5 0u1
0603
4
3
8
R5 9k09
0402
2
C10
1u
1
0603
C4
2n2
0402
C3
0u1
0603
C1
10u
1210
L1 2u2
7
VTT
2525
C6
+
R8 0R
0402
220u/15mOhm
7343
.igure 3: Reference Design and Layout Example for VBAT = 8V to 20V, VTT = 0.9V, 3A
Note R8 is present to facilitate isolation of power ground and VSSA during layout.
2003 Semtech Corp.
14
www.semtech.com
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