MAX1237 Ver la hoja de datos (PDF) - Maxim Integrated

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MAX1237

2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

Maxim Integrated 

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

Table 5. Scanning Configuration

SCAN1 SCAN0

SCANNING CONFIGURATION

Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 11, the scanning stops

0

0

at AIN11. When AIN_/REF is set to be a REF in/out, scanning stops at AIN10 or AIN3.

0

1

*Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).

Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0–AIN2,

the scanning stops at AIN2 (MAX1236/MAX1237). When AIN/REF is set to be a REF IN/OUT, scanning

1

0

stops at AIN3 or AIN10.

Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0-AIN6, scanning

stops at AIN6 (MAX1238/MAX1239). When AIN/REF is set to be a REF IN/OUT, scanning stops at AIN or

AIN10.

1

1

*Converts channel selected by CS3–CS0.

*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting occurs

perpetually until not-acknowledge occurs.

clock. In external clock mode, the MAX1236–MAX1239

begin tracking the analog input on the ninth rising clock

edge of a valid slave address byte. Two SCL clock

cycles later, the analog signal is acquired and the con-

version begins. Unlike internal clock mode, converted

data is available immediately after the first four empty

high bits. The device continuously converts input chan-

nels dictated by the scan mode until given a not

acknowledge. There is no need to readdress the

device with a read command to obtain new conversion

results (see Figure 11).

The conversion must complete in 1ms, or droop on the

track-and-hold capacitor degrades conversion results.

Use internal clock mode if the SCL clock period

exceeds 60µs.

The MAX1236–MAX1239 must operate in external clock

mode for conversion rates from 40ksps to 94.4ksps.

Below 40ksps, internal clock mode is recommended

due to much smaller power consumption.

Scan Mode

SCAN0 and SCAN1 of the configuration byte set the

scan mode configuration. Table 5 shows the scanning

configurations. If AIN_/REF is set to be a reference

input or output (SEL1 = 1, Table 6), AIN_/REF is exclud-

ed from a multichannel scan. The scanned results are

written to memory in the same order as the conversion.

Read the results from memory in the order they were

converted. Each result needs a 2-byte transmission; the

first byte begins with four empty bits, during which SDA

is left high. Each byte has to be acknowledged by the

master or the memory transmission is terminated. It is

not possible to read the memory independently of con-

version.

Applications Information

Power-On Reset

The configuration and setup registers (Tables 1 and 2)

default to a single-ended, unipolar, single-channel con-

version on AIN0 using the internal clock with VDD as the

reference and AIN_/REF configured as an analog input.

The memory contents are unknown after power-up.

Automatic Shutdown

SEL[2:0] of the setup byte (Table 1 and Table 6) control

the state of the reference and AIN_/REF. If automatic

shutdown is selected (SEL[2:0] = 100), shutdown

occurs between conversions when the MAX1236–

MAX1239 are idle. When operating in external clock

mode, a STOP, not-acknowledge, or repeated START

condition must be issued to place the devices in idle

mode and benefit from automatic shutdown. A STOP

condition is not necessary in internal clock mode to

benefit from automatic shutdown because power-down

occurs once all contents are written to memory (Figure

10). All analog circuitry is inactive in shutdown and

supply current is less than 0.5µA. The digital conversion

results are maintained in memory during shutdown and

are available for access through the serial interface at

any time prior to a STOP or a repeated START condition.

When idle, the MAX1236–MAX1239 continuously wait

for a START condition followed by their slave address

(see the Slave Address section). Upon reading a valid

address byte, the MAX1236–MAX1239 power up. The

internal reference requires 10ms to wake up, so when

using the internal reference it should be powered up

10ms prior to conversion or powered continuously.

Wake-up is invisible when using an external reference

or VDD as the reference.

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