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OR3C55-4S240

ORCA® Series 3C and 3T Field-Programmable Gate Arrays

Agere -> LSI Corporation 

ORCA Series 3C and 3T FPGAs

Data Sheet

June 1999

Programmable Input/Output Cells (continued)

Input Demultiplexing

The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing

provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration

and general timing for demultiplexing a multiplexed address and data signal. The PIO input signal is sent to both

the input latch and directly to IN2. The signal is latched on the falling edge of the clock and output to routing at IN1.

The address and data are then both available at the rising edge of the system clock. These signals may be regis-

tered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the possible use of the SLIC

decoder to perform an address decode to enable which registers are to receive the input data. Although the timing

shown is for using the input register as a latch, it may also be used in the same way as an FF. Also note that the sig-

nals found in PIO inputs IN1 and IN2 can be interchanged.

PAD

OTHER ADDRESS

LINES

PIO

PLC

D Q IN1

DEC

SLIC

SCLK

IN2

DQ

CE

SCLK

PIO INPUT

DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4 DATA4 ADDR5

PIO LATCH

OUTPUT

ADDR1

PLC FF

OUTPUT

DATA0

ADDR2

DATA1

ADDR3

DATA2

ADDR4

ADDR5

DATA3

DATA4

Figure 24. PIO Input Demultiplexing

5-5798(F)

40

Lucent Technologies Inc.

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