CXA3268AR Ver la hoja de datos (PDF) - Sony Semiconductor

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CXA3268AR

Driver/Timing Generator for Color LCD Panels

Sony Semiconductor 

CXA3268AR

Notes on Operation

(1) This IC contains digital circuits, so the set board pattern must be designed in consideration of undesired

radiation, interference to analog circuits, etc. Care should also be taken for the following items when

designing the pattern.

• The digital and analog IC power supplies should be separated, but the GND and VSS should not be

separated and should use a plain GND (VSS) pattern in order to reduce impedance as much as possible.

The power supplies should also use a plain pattern.

• Use ceramic capacitors for the by-pass capacitors between the power supplies and GND, and connect

these capacitors as close to the pins as possible.

• The resistor connected to Pin 8 should be connected as close to the pin as possible, and the wiring from

the pin to GND should be as short as possible. Also, do not pass other signal lines close to this pin or the

connected resistor.

• The resistor connected to Pin 17 should be located as close to the pin as possible. Also, do not pass

other signal lines close to this pin.

• The capacitors connected to Pins 7 and 42 should be located as close to the LCD panel as possible.

• The PLL block (LPF/VCO) should be compact and located near the IC.

(2) The R/R-Y (Pin 72), G/Y (Pin 71), B/B-Y (Pin 70) and FIL IN (Pin 69) pin input signals are clamped at the

inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low

impedance.

(Input at an impedance of 1kΩ (max.) or less.)

(3) The smoothing capacitor of the DC level control feedback circuit in the capacitor block connected to the

RGB output pins should have a leak current with a small absolute value and variance. Also, when using the

pulse elimination (PAL display, WIDE display) function, the picture quality should be thoroughly evaluated

before deciding the capacitance value of the capacitor.

(4) A thorough study of whether the capacitor connected to the COM output pin satisfies the LCD panel

specifications should be made before deciding the capacitance value.

(5) If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction

depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of

using this IC with other circuits before deciding on its use.

(6) Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than

the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to

the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up.

(7) Be sure to observe the power supply and power saving sequence specifications specified for this IC.

(8) Do not apply a voltage higher than VDD or lower than VSS to I/O pins.

(9) Do not use this IC under operating conditions other than those given.

(10) Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may

damage the device, leading to eventual breakdown.

(11) This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should

be taken to prevent electrostatic discharge.

(12) Always connect the VSS, GND1 and GND2/3 pins to the lowest potential applied to this IC; do not leave

these pins open. The voltages applied to the power supply pins should be as follows.

VSS = GND1 = GND2/3 ≤ VDD = VCC1 ≤ VCC2 = VCC3.

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