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AD641A Datasheet PDF : 17 Pages
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AD641
Using Higher Supply Voltages
The AD641 is calibrated using ± 5 V supplies. Scaling is very
insensitive to the supply voltages and higher supply voltages will
not directly cause significant errors. However, the AD641 power
dissipation must be kept below 500 mW in the interest of reli-
ability and long term stability. When using well regulated supply
voltages above ± 6 V, the decoupling resistors shown in the
application schematics can be increased to maintain ± 5 V at the
IC. The resistor values are calculated using the specified maxi-
mum of 15 mA current into the +VS terminal (Pin 12) and a
maximum of 60 mA into the –VS terminal (Pin 7). For example,
when using ± 9 V supplies, a resistor of (9 V – 5 V)/15 mA, about
261 Ω, should be included in the +VS lead to each AD641 and
(9 V – 5 V)/60 mA, about 64.9 Ω in each –VS lead. Of course,
asymmetric supplies may be dealt with in a similar way.
Using the Attenuator
In applications where the signal amplitude is sufficient, the on-
chip attenuator should be used because it provides a tempera-
ture independent dynamic range (compare Figures 18 and 19).
Figure 26 shows this attenuator in more detail. R1 is a thin-film
SIG ATN
+IN OUT
20 19 18 17 16
R1
R2
R3
FIRST
AMPLIFIER
R4
1
2
3
4
5
ATN
SIG ATN ATN ATN IN
–IN LO COM COM
INPUT
Figure 26. Details of the Input Attenuator
resistor of nominally 270 Ω and low temperature coefficient
(TC). It is trimmed to calibrate the intercept to 10 mV dc (or
–24 dBm for sinusoidal inputs), that is, to an attenuation of
nominally 20 dBs at +27°C. R2 has a nominal value of 30 Ω and
has a high positive TC, such that the overall attenuation factor
is 0.33%/°C at +27°C. This results in a transmission factor that is
proportional to absolute temperature, or PTAT. (See Intercept
Stabilization for further explanation.) To improve the accuracy
of the attenuator, the ATN COM nodes are bonded to both Pin
3 and Pin 4. These should be connected directly to the “SlGNAL
LOW” of the source (for example, to the grounded side of the
signal connector, as shown in Figure 32) not to an arbitrary
point on the ground plane.
R4 is identical to R2, and in shunt with R3 (270 Ω thin film)
forms a 27 Ω resistor with the same TC as the output resistance
of the attenuator. By connecting Pin 1 to ATN LOW (Pin 2)
this resistance minimizes the offset caused by bias currents. The
offset nulling scheme shown in Figure 25 may still be used, with
the external resistor RB omitted and ROS = 500 kΩ. Offset stabil-
ity is improved because the compensating voltage introduced at
Pin 20 is now PTAT. Drifts of under 1 µV/°C (referred to Pins
1 and 20) can be maintained using the attenuator.
It may occasionally be desirable to attenuate the signal even
further. For example, the source may have a full-scale value of
± 10 V, and since the basic range of the AD641 extends only to
± 200 mV dc, an attenuation factor of ×50 might be chosen.
This may be achieved either by using an independent external
attenuator or more simply by adding a resistor in series with
ATN IN (Pin 5). In the latter case the resistor must be trimmed
to calibrate the intercept, since the input resistance at Pin 5 is
not guaranteed. A fixed resistor of 1 kΩ in series with a 500 Ω
variable resistor calibrate to an intercept of 50 mV (or –26 dBV)
for dc or square wave inputs and provide a ± 10 V input range.
The intercept stability will be degraded to about 0.003 dB/°C.
DENOTES A CONNECTION TO THE
GROUND PLANE; OBSERVE COMMON
CONNECTIONS WHERE SHOWN.
ALL UNMARKED CAPACITORS ARE
0.1F CERAMIC. FOR VALUES OF
NUMBERED COMPONENTS SEE TEXT
SIGNAL
INPUT
10⍀
C1
10⍀
20 19 18 17 16 15 14 13 12 11
SIG
+IN
ATN CKT RG1 RG0 RG2
OUT COM
LOG
OUT
LOG
COM
+VS
SIG
+OUT
1k⍀ 1k⍀
U1 AD641
R1
SIG ATN ATN ATN ATN
SIG
–IN LO COM COM IN BL1 –VS ITC BL2 –OUT
1 2 3 4 5 6 7 8 9 10
R2
NC
10⍀
10⍀
1mA/DECADE
+5V
OUTPUT
–50mV/DECADE
C2
NC
20 19 18 17 16 15 14 13 12 11
SIG
+IN
ATN CKT RG1 RG0 RG2
OUT COM
LOG
OUT
LOG
COM
+VS
SIG
+OUT
1k⍀ 1k⍀
U2 AD641
SIG ATN ATN ATN ATN
SIG
–IN LO COM COM IN BL1 –VS ITC BL2 –OUT
1 2 3 4 5 6 7 8 9 10
NC
C3 RL = 50⍀
4.7⍀
4.7⍀
–5V
Figure 27. Basic Connections for Cascaded AD641s
–12–
REV. D
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