CXP5078 Ver la hoja de datos (PDF) - Sony Semiconductor
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CXP5078 Datasheet PDF : 18 Pages
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CXP5076/5078
(2) Serial transfer
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
Serial transfer clock (SC) tKCY
SC
Input mode
tsys/4 + 1.42
µs
cycle time
Output mode
2tsys
µs
Input mode
tsys/8 + 0.7
µs
Serial transfer clock (SC) tKH
high and low level widths tKL
SC
Output mode∗1
tsys – 0.1
µs
Output mode∗2
tsys – 1.6
µs
Serial data input setup
time (against SC ↑)
tSIK
SI
SC input mode
0.1
SC output mode
0.2
µs
µs
Serial data input hold
time (against SC ↑)
tKSI
SI
SC input mode
SC output mode
tsys/8 + 0.5
0.1
µs
µs
High data output delay
time from SC falling∗3
tKSO
SO
tsys/8 + 0.5 µs
High data output delay
time from SC falling∗4
tKSO
SO
tsys/8 + 1.6 µs
Low data output delay
time from SC falling
tKSO
SO
tsys/8 + 0.5 µs
Notes) 1. tsys in the EXTAL input clock is 8/fc. (It is impossible to use in TEX input clock.)
2. The load of data output delay is 50pF + 1TTL.
∗1 It is specified when PX0/SC pin is selected to the tri-state output by the program.
∗2 It is specified when PX0/SC pin is selected to the pull-up resistance by the program.
As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock
frequency fc.
∗3 This item is specified when PX1/SO pin is selected to the tri-state output by the program.
∗4 This item is specified when PX1/SO pin is selected to the pull-up resistance by the program.
tKCY
tKL
tKH
0.8VDD
SC
0.2VDD
tSIK
tKSI
0.8VDD
SI
Input data
0.2VDD
tKSO
0.8VDD
SO
Output data
0.2VDD
Fig. 5. Serial transfer timing
– 13 –
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