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XR16C2852
(Rev.:2002)

3.3V AND 5V DUART WITH 128-BYTE FIFO

Exar Corporation 

XR16C2852

REV. 2.0.0

3.3V AND 5V DUART WITH 128-BYTE FIFO

áç

NAME

GND

44-PLCC

PIN #

22, 12

TYPE

Pwr Power supply common, ground.

DESCRIPTION

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

1.0 PRODUCT DESCRIPTION

The XR16C2852 (2852) integrates the functions of 2

enhanced 16C550 Universal Asynchrounous Receiv-

er and Transmitter (UART). Each UART is indepen-

dently controlled having its own set of device configu-

ration registers. The configuration registers set is

16550 UART compatible for control, status and data

transfer. Additionally, each UART channel has 128-

bytes of transmit and receive FIFOs, automatic RTS/

CTS hardware flow control with hysteresis control,

automatic Xon/Xoff and special character software

flow control, programmable transmit and receive

FIFO trigger levels, FIFO level counters, infrared en-

coder and decoder (IrDA ver 1.0), programmable

baud rate generator with a prescaler of divide by 1 or

4, and data rate up to 3.125 Mbps. The XR16C2852

is a 5V and 3.3V device. The 2852 is fabricated with

an advanced CMOS process.

Enhanced Features

The 2852 DUART provides a solution that supports

128 bytes of transmit and receive FIFO memory, in-

stead of 64 bytes provided in the XR16L2752 and 16

bytes in the ST16C2552. The 2852 is designed to

work with high performance data communication sys-

tems, that require fast data processing time. In-

creased performance is realized in the 2852 by the

larger transmit and receive FIFOs, FIFO trigger level

control, FIFO level counters and automatic flow con-

trol mechanism. This allows the external processor to

handle more networking tasks within a given time. For

example, the ST16C2552 with a 16 byte FIFO, un-

loads 16 bytes of receive data in 1.53 ms (This exam-

ple uses a character length of 11 bits, including start/

stop bits at 115.2Kbps). This means the external

CPU will have to service the receive FIFO at 1.53 ms

intervals. However with the 128 byte FIFO in the

2852, the data buffer will not require unloading/load-

ing for 12.2 ms. This increases the service interval

giving the external CPU additional time for other ap-

plications and reducing the overall UART interrupt

servicing time. In addition, the programmable FIFO

level trigger interrupt and automatic hardware/soft-

ware flow control is uniquely provided for maximum

data throughput performance especially when operat-

ing in a multi-channel system. The combination of the

above greatly reduces the CPU’s bandwidth require-

ment, increases performance, and reduces power

consumption.

The 2852 supports a half-duplex output direction con-

trol signaling pin, RTS# A/B, to enable and disable

the external RS-485 transceiver operation. It auto-

matically switches the logic state of the output pin to

the receive state after the last stop-bit of the last char-

acter has been shifted out of the transmitter. After re-

ceiving, the logic state of the output pin switches back

to the transmit state when a data byte is loaded in the

transmitter. The auto RS-485 direction control pin is

not activated after reset. To activate the direction con-

trol function, user has to set FCTR Bit-3 to “1”. This

pin is normally high for receive state, low for transmit

state.

Data Rate

The 2852 is capable of operation up to 3.125Mbps at

5V with 16x internal sampling clock rate. The device

can operate with an external 24 MHz crystal on pins

XTAL1 and XTAL2, or external clock source of up to

50MHz on XTAL1 pin. With a typical crystal of

14.7464 MHz and through a software option, the user

can set the prescaler bit for data rates of up to

921.6Kbps.

The rich feature set of the 2852 is available through

the internal registers. Automatic hardware/software

flow control, selectable transmit and receive FIFO

trigger levels, selectable TX and RX baud rates, infra-

red encoder/decoder interface, modem interface con-

trols, and a sleep mode are all standard features.

Following a power on reset or an external reset, the

2852 is software compatible with previous generation

of UARTs, 16C2552 and 16L2752.

5

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