CXP402 Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXP402 Datasheet PDF : 16 Pages
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CXP402
Pin Description
Symbol
I/O
Description
PA0 to PA3
I/O
(Port A)
4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is
attached for input. (4 pins)
PB0 to PB3
I/O
(Port B)
4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is
attached for input. (4 pins)
PC0 to PC3
I/O
(Port C)
4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is
attached for input. (4 pins)
SEG0 to SEG15 Output
LCD segment signal output. (16 pins)
COM0 to COM3 Output
LCD common signal output.
VLC1 to VLC3
LCD bias power supply. Bias voltage is generated, which is 1/3 the
supply voltage due to the internal resistor. (3 pins)
SEIN
Input
SENS input from SSP.
CNIN
Input
Track jump count signal input.
DATO
Output
Serial data output to SSP.
XLTO
Output
Serial data latch output to SSP.
CLKO
Output
Serial clock output to SSP.
MON
Output
Spindle motor ON/OFF control output.
MDP
MDS
Output
(tri-state)
Spindle motor servo control. (2 pins)
LOCK
Output
Lock signal output. GFS is sampled at 460Hz and; when GFS is high,
this pin outputs a high signal. If GFS is low eight convective samples,
this pin outputs low.
VPCO1
VPCO2
Output
(tri-state)
Wide-band EFM PLL charge pump output. (2 pins)
VCKI
Input
Wide-band EFM PLL VCO2 oscillation input.
V16M
Output
Wide-band EFM PLL VCO2 oscillation output.
VCTL
Input
Wide-band EFM PLL VCO2 control voltage input.
PCO
Output (tri-state) Master PLL charge pump output.
FILI
Input
Master PLL filter input.
FILO
Output (Analog) Master PLL filter output.
CLTV
Input
Master VCO control voltage input.
RF
Input
EFM signal input.
BIAS
Input
Asymmetry circuit constant current input.
ASYI
Input
Asymmetry comparator voltage input.
ASYO
Output
EFM output. (full swing)
XRST
Input
System reset input. Active at low.
–4–
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