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NJU6631A Ver la hoja de datos (PDF) - Japan Radio Corporation

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NJU6631A Datasheet PDF : 32 Pages
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NJU6631A
(2) Power on Initialization by internal circuits
(2-1) Initialization by Internal Reset circuits
The NJU6631A is automatically initialized by internal power on initialization circuits when the power is turned
on. In the internal power on initialization, following instructions are executed.
During the Internal power on initialization, the busy flag (BF) is "1" and this status is kept 10 ms after VDD
rises to 4.5V.
Initialization flow is shown below :
Clear Display
Function Set
Display On/Off
Control
DL=1 : 8-bit long interface data
A=0 : Addressing mode 1
M0=0 : Pin configuration mode A
M1=0 : 16-Character 1-Line
D=0 : Display Off
C=0 : Cursor Off
B=0 : Cursor Blink Off
NOTE
If the condition of power supply rise
time described in the Electrical
Characteristics is not satisfied, the
internal Power On Initialization
Circuits will not operate and
initialization will not be performed.
In this case the initialization by MPU
software is required.
Entry Mode Set
I/D=1 : Increment by 1
S=0 : No Shift
(2-2) Initialization by Hardware
The NJU6631A incorporates RESET terminal to initialize the all system. When the "L" level input over
1.2ms to the RESET terminal, reset sequence is executed. In this time, busy signal output during 10ms after
RESET terminal goes to "H".
- Reset Circuit
RESET
System Clock
C Counter Q
RST
- Timing Chart
External Reset
Signal
Counter Output
Power On Reset
Over than
1.2ms
SQ
R
RS-F/F
System Reset
RS-F/F Output
Internal Reset
Signal
Busy
10ms

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