M4A3-384/256-55JNC Ver la hoja de datos (PDF) - Lattice Semiconductor

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M4A3-384/256-55JNC

High Performance E2CMOS® In-System Programmable Logic

Lattice Semiconductor 

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128)

Bottom View

256-Ball fpBGA

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

TRST

I/O117

O5

I/O116

O4

I/O113

O1

I/O126

P6

I/O124

P4

I12

NC

NC

NC

CLK0

I/O1

A1

I/O5

A5

I/O7

A7

I/O10

B2

I/O12

B4

A

B

I/O110

N6

I/O111

N7

I/O118

O6

I/O115

O3

I/O127

P7

I/O125

P5

I/O120

P0

NC

NC

NC

I1

I/O2

A2

I/O8 I/O11 I/O13

B0

B3

B5

NC B

C

I/O108

N4

I/O109

N5

NC

I/O119 I/O114 I/O122 I/O123

O7

O2

P2

P3

NC

NC

I0

I/O4

A4

I/O6

A6

I/O15 I/O14

B7

B6

TDI

I/O23

C7

C

D

NC

I/O104

N0

TDO

GND

GND

VCC

GND

VCC

GND

GND

VCC

GND

VCC

I/O9

B1

I/O22

C6

I/O21

C5

D

E

I/O102

M6

NC

I/O107

N3

VCC

I/O105 I/O106

N1

N2

I13

CLK3

NC

NC

I/O0

A0

NC

GND

I/O20

C4

I/O19

C3

I/O31

D7

E

F

I/O98

M2

I/O103 I/O101

M7

M5

GND

I/O100

M4

I/O99

M3

I/O112 I/O121

O0

P1

NC

NC

I/O3

A3

I/O18

C2

VCC

I/O16

C0

I/O30

D6

I/O29

D5

F

G NC

I/O96

M0

I11

VCC

NC

I/O97

M1

VCC

GND

GND

VCC

I/O17 I/O28

C1

D4

GND

I/O26 I/O25

D2

D1

I2 G

H

I/O88

L0

I10

I9

GND

I/O89

L1

I/O90

L2

GND

VCC

VCC

GND

I/O27

D3

I/O24

D0

VCC

NC

NC

NC H

J

I/O91

L3

I/O92

L4

I/O93

L5

GND

I/O95

L7

I/O94

L6

GND

VCC

VCC

GND

I3

NC

GND

NC

NC

NC J

K NC

NC

NC

VCC

NC

NC

VCC GND GND VCC

NC

NC

VCC

I4

NC

I/O32

E0

K

L NC

NC

I/O80

K0

GND

I/O83

K3

NC

NC

NC

I/O59 I/O61

H3

H5

NC

NC

GND

I/O35

E3

I/O36

E4

I/O33

E1

L

M

I/O81

K1

I/O82

K2

I/O84

K4

GND

I/O67

I3

I/O65

I1

NC

NC

I/O58 I/O48 I/O51

H2

G0

G3

NC

VCC

I/O44

F4

I/O39

E7

I/O34

E2

M

N

I/O85

K5

I/O86 ENABLE

K6

VCC

GND

VCC

GND

VCC

GND

GND

VCC

GND

GND

TCK

I/O40

F0

I/O37

E5

N

P

I/O87

K7

I/O77

J5

I/O78

J6

I/O79

J7

I/O68

I4

I/O66

I2

NC

NC

NC

I6

I/O63

H7

I/O52

G4

I/O55

G7

TMS

I/O41

F1

I/O38

E6

P

R

I/O76

J4

I/O75

J3

I/O72

J0

I/O71

I7

I/O64

I0

I7

NC

NC

NC

I/O56

H0

I/O60

H4

I/O49

G1

I/O53

G5

I/O47

F7

I/O43

F3

I/O42

F2

R

T

I/O74

J2

I/O73

J1

I/O70

I6

I/O69

I5

I8

CLK2 NC

NC CLK1

I5

16 15 14 13 12 11 10

9

8

7

PIN DESIGNATIONS

CLK

= Clock

GND = Ground

I

= Input

I/O

= Input/Output

N/C

= No Connect

VCC

= Supply Voltage

TDI

= Test Data In

TCK

= Test Clock

TMS

= Test Mode Select

TDO

= Test Data Out

TRST = Test Reset

ENABLE = Program

C7

I/O57

H1

I/O62

H6

I/O50

G2

I/O54

G6

I/O46

F6

I/O45

F5

T

6

5

4

3

2

1

I/O Cell

PAL Block

m4a3.256.128_256bga

56

ispMACH 4A Family

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