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DSP1620

DSP1627 Digital Signal Processor

Agere -> LSI Corporation 

DSP1628 Digital Signal Processor

Preliminary Data Sheet

February 1997

4 Hardware Architecture (continued)

DB[15:0] AB[15:0] RWN EXM I/O EROM ERAMHI ERAMLO

ioc

EXTERNAL MEMORY INTERFACE & EMUX

CKI

CKI2

CKO

RSTB

STOP

TRAP

INT[1:0]

IACK

VEC[3:0] OR IOBIT[7:4]

DO2 OR PSTAT

OLD2 OR PODS

OCK2 OR PCSN

OBE2 OR POBE

SYNC2 OR PBSEL

ICK2 OR PB0

ILD2 OR PIDS

DI2 OR PB1

IBF2 OR PIBF

DOEN2 OR PB2

SADD2 OR PB3

IO BIT[3:0] OR PB[7:4]

ROM

48K x 16

DUAL-PORT

RAM

[16/8:5,3:1]

15/7K x 16†

XAB XDB YAB YDB

DSP1600 CORE

IDB

PHIF

phifc

PSTAT*

powerc

M

pdx0(IN)

U

X

pdx0(OUT)

BIO

sbit

cbit

RAM4

1K x 16†

ECCP

eir

ear

edr

BMU

aa0

aa1

ar0

ar1

ar2

ar3

pllc

SIO2

sdx2(OUT)

srta2

tdms2

sdx2(IN)

sioc2

saddx2

JTAG

BOUNDARY SCAN*

jtag

JCON*

ID*

BYPASS*

HDS

BREAK POINT*

TRACE*

TIMER

timerc

timer0

SIO

sdx(OUT)

srta

tdms

sdx(IN)

sioc

saddx

TDO

TDI

TCK

TMS

TRST

DI1

ICK1

ILD1

IBF1

DO1

OCK1

OLD1

OBE1

SYNC1

SADD1

DOEN1

* These registers are accessible through the pins only.

† 16K x 16 for the DSP1628x16, 8K x 16 for the DSP1628x08.

Figure 4. DSP1628 Block Diagram

5-4142 (F).f

10

Lucent Technologies Inc.

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