VIPER100BSP Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

VIPER100BSP

SMPS PRIMARY I.C.

STMicroelectronics 

VIPER100B/BSP

placed into a standby mode with reduced

consumption and also provided to the external

capacitor connected to the VDD pin. As soon as

the voltage on this pin reaches the high voltage

threshold VDDon of the UVLO logic, the device

turns into active mode and starts switching. The

start up current generator is switched off, and the

converter should normally provide the needed

current on the VDD pin through the auxiliary

winding of the transformer, as shown on figure

15.

In case of abnormal condition where the auxiliary

winding is unable to provide the low voltage

supply current to the VDD pin (i.e. short circuit on

the output of the converter), the external

capacitor discharges itself down to the low

threshold voltage VDDoff of the UVLO logic, and

the device get back to the inactive state where

the internal circuits are in standby mode and the

start up current source is activated. The converter

enters a endless start up cycle, with a start-up

duty cycle defined by the ratio of charging current

towards discharging when the VIPer100B/BSP

tries to start. This ratio is fixed by design to 2 to

15, which gives a 12% start up duty cycle while

the power dissipation at start up is approximately

0.6 W, for a 230 Vrms input voltage. This low

value of start-up duty cycle prevents the stress of

the output rectifiers and of the transformer when

in short circuit.

The external capacitor CVDD on the VDD pin must

be sized according to the time needed by the

converter to start up, when the device starts

switching. This time tSS depends on many

parameters, among which transformer design,

output capacitors, soft start feature and

compensation network implemented on the

COMP pin. The following formula can be used for

defining the minimum capacitor needed:

CVDD

>

IDD tSS

VDDhyst

where:

IDD is the consumption current on the VDD pin

when switching. Refer to specified IDD1 and IDD2

values.

tSS is the start up time of the converter when the

device begins to switch. Worst case is generally

at full load.

VDDhyst is the voltage hysteresis of the UVLO

logic. Refer to the minimum specified value.

Soft start feature can be implemented on the

COMP pin through a simple capacitor which will

be also used as the compensation network. In

this case, the regulation loop bandwidth is rather

low, because of the large value of this capacitor.

In case a large regulation loop bandwidth is

mandatory, the schematics of figure 16 can be

Figure 15: Behaviour of the high voltage current source at start-up

VDD

VDDo n

VDDoff

2 mA VDD

15 mA

1 mA 15 mA

3 mA

CVDD

Ref.

t

UNDERVOLTAGE

Auxiliary primary

LOCK OUT LOGIC

winding

VIP er100B

DRAIN

S O UR C E

Sta rt up duty cycle ~ 10%

FC001 00 B

13/20

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