HM658512ALP-7V Ver la hoja de datos (PDF) - Hitachi -> Renesas Electronics
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HM658512ALP-7V Datasheet PDF : 22 Pages
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HM658512A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) (cont.)
HM658512A
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-8
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Parameter
Symbol Min Max Min Max Min Max Unit Notes
Data in to end of write
t DW
Data in hold time for write
t DH
Output active from end of write
t OW
Write to output in high-Z
t WHZ
Transition time (rise and fall)
tT
Refresh command delay time
t RFD
Refresh precharge time
t FP
Refresh command pulse width for tFAP
automatic refresh
20 —
20 —
25 —
ns
0—
0
—
0—
ns
5—
5
—
5—
ns 2
— 20
— 20
— 25
ns 1, 2
3
50
3
50
3
50
ns 6
35 —
40 —
50 —
ns
35 —
40 —
40 —
ns
70 n 8 µ 80 n 8 µ 80 n 8 µ s
Automatic refresh cycle time
t FC
Refresh command pulse width for tFAS
self refresh
115 —
130 —
160 —
ns
8—
8
—
8—
µs
Refresh reset time from self refresh tRFS
Refresh period
t REF
600 —
— 32
600 —
— 32
600 —
— 32
ns 9
ms 2048
cycle
Notes: 1. tCHZ, tOHZ, tWHZ are defined as the time at which the output achieves the open circuit condition.
2. tCHZ, tCLZ, tOHZ, tOLZ, tWHZ and tOW are sampled under the condition of tT = 5 ns and not 100% tested.
3. A write occurs during the overlap of low CE and low WE. Write end is defined at the earlier of
WE going high or CE going high.
4. If the CE low transition occurs simultaneously with or from the WE low transition, the output
buffers remain in high impedance state.
5. In write cycle, OE or WE must disable output buffers prior to applying data to the device and at
the end of write cycle data inputs must be floated prior to OE or WE turning on output buffers.
During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.
6. Transition time tT is measured between VIH (min) and VIL (max). VIH (min) and VIL (max) are
reference levels for measuring timing of input signals.
7. After power-up, pause for more than 100 µs and execute at least 8 initialization cycles.
8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed
within 15 µs after self refresh, in order to meet the refresh specification of 32 ms and 2048
cycles.
9. At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh
operation of the RAM. During tRFS, CE and OE/RFSH must be kept high. If automatic refresh
follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not
occur during tRFS period.
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