CXA3276Q Ver la hoja de datos (PDF) - Sony Semiconductor

Número de pieza

componentes Descripción

Fabricante

CXA3276Q

8-bit 160MSPS Flash A/D Converter

Sony Semiconductor 

CXA3276Q

Notes on Operation

• The CXA3276Q has the PECL and TTL input pins for the clock and reset input pins. When the clock is input

in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL

level, inputting the reset signal in TTL is recommended.

• The impedance of the input signal should be properly matched to ensure the CXA3276Q's stable operation at

high speed.

• The power supply and grounding have a profound influence on converter performance. The power supply

and grounding method are particularly important during high-speed operation. General points for caution are

as follows.

— The ground pattern should be as large as possible. It is recommended to make the power supply and

ground patterns wider at an inner layer using a multi-layer board.

— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the

respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc

and DVcc lines at one point each via a ferrite-bead filter, etc. Shorting the AGND and DGND patterns in

one place immediately under the A/D converter improves A/D converter performance.

— Be sure to turn the analog and digital power supplies on simultaneously. If not simultaneously, the IC does

not operate correctly.

— Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a

0.1µF or larger ceramic chip capacitor.

(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.)

— It is recommended to place the ceramic chip capacitor of 0.1µF or more, in particular, between DVcc2

and DGND2 with the shortest distance.This has the effect to suppress the noise generated when the

CXA3276Q TTL output circuit operates.

— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring

capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output

waveform since the original output slew rate is quite fast.

• The analog input pin VIN has an input capacitance of approximately 10pF. To drive the A/D converter with the

proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance

or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using

chip parts for resistors and capacitors, etc.

• The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them

to AGND with approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible.

• If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,

approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as the threshold

voltage VBB because it is too weak.

• When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When

the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open.

• The CXA3276Q TTL output high level is clamped to approximately 2.8 V in the IC.This makes it possible to

directly interface with the 3.3V system CMOS IC.

• The CXA3026AQ has the output pins P1∗∗ and P2∗∗. However, in the CXA3276Q, these symbols are

changed as PA∗∗and PB∗∗. At this time, the P1 side of the CXA3026AQ is changed to the PB side for the

CXA3276Q; the P2 side of the CXA3026AQ to the PA side for the CXA3276Q.

• The pipeline delay of the CXA3276Q is smaller by one clock, compared to that of CXA3026AQ.

– 19 –

Share Link: