CXA3276Q
When the reset signal is not used
CLK
CLK
CXA3276Q
CLK A A
RESETN
CLKOUT
8bit
DATA
CXA3276Q
CLK B B
RESETN
CLKOUT
8bit
DATA
When the reset signal is used
CLK
CXA3276Q
CLK
A
RESETN
CLK
Reset signal
CLKOUT
8bit
DATA
(Reset period)
Reset signal
CXA3276Q
CLK
B
RESETN
CLKOUT
8bit
DATA
(Reset period)
2. Straight mode (See Application Circuits 1-(4), (5) and (6).)
Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the
clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter
as the system clock.
The A/D converter can operate at Fc (min.) = 125MSPS in this mode.
Digital input level and supply voltage settings
The logic input level for the CXA3276Q supports ECL, PECL and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and
reset signals) level.
Digital input level
ECL
PECL
TTL
DVEE3
–5V
0V
0V
DGND3
0V
+5V
+5V
Supply voltage Application circuits
±5V
(1) (4)
+5V
(2) (5)
+5V
(3) (6)
Table 3. Logic Input Level and Power Supply Settings
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