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Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Fig. 15 Interrupt control
MITSUBISHI MICROCOMPUTERS
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT2/Key input interrupt switch bit
Timer Y/CNTR1 interrupt switch bit
Not used (return “0” when read)
(Do not write to “1”)
0 : Falling edge active
1 : Rising edge active
0 : INT2 interrupt
1 : Key input interrupt
0 : Timer Y interrupt
1 : CNTR1 interrupt
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16)
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Key input interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
CNTR0 interrupt request bit
Timer Y interrupt request bit
CNTR1 interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16)
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Key input interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
CNTR0 interrupt enable bit
Timer Y interrupt enable bit
CNTR1 interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write to “1”.)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers
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