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M38C21F1DHP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

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MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by nineteen sources: six external, twelve internal,

and one software.

Interrupt Control

Each interrupt except the BRK instruction interrupt have both an in-

terrupt request bit and an interrupt enable bit, and is controlled by the

interrupt disable flag. An interrupt occurs if the corresponding inter-

rupt request and enable bits are “1” and the interrupt disable flag is

“0”.

Interrupt enable bits can be set or cleared by software. Interrupt re-

quest bits can be cleared by software, but cannot be set by software.

The BRK instruction interrupt and reset cannot be disabled with any

flag or bit. The I flag disables all interrupts except the BRK instruction

interrupt and reset. If several interrupts requests occurs at the same

time the interrupt with highest priority is accepted first.

Interrupt Operation

By acceptance of an interrupt, the following operations are automati-

cally performed:

1. The processing being executed is stopped.

2. The contents of the program counter and processor status reg-

ister are automatically pushed onto the stack.

3. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

4. The interrupt jump destination address is read from the vector

table into the program counter.

s Notes on Interrupts

When the active edge of an external interrupt (INT0 – INT2, CNTR0

or CNTR1) is set or an interrupt source where several interrupt source

is assigned to the same vector address is switched, the correspond-

ing interrupt request bit may also be set. Therefore, take following

sequence:

(1) Disable the interrupt.

(2) Set the interrupt edge selection register (Timer X control reg-

ister for CNTR0, Timer Y mode register for CNTR1).

(3) Clear the set interrupt request bit to “0.”

(4) Enable the interrupt.

Table 7 Interrupt vector addresses and priority

Vector Addresses (Note 1)

Interrupt Source Priority

High

Low

Interrupt Request

Generating Conditions

Remarks

Reset (Note 2)

1

FFFD16

FFFC16 At reset

Non-maskable

INT0

2

FFFB16

FFFA16 At detection of either rising or falling External interrupt (active edge selectable)

edge of INT0 input

INT1

3

FFF916

FFF816 At detection of either rising or falling External interrupt (active edge selectable)

edge of INT1 input

INT2

4

FFF716

FFF616 At detection of either rising or falling Valid when INT2 interrupt is selected

edge of INT2 input

External interrupt (active edge selectable)

Key input

(key-on wakeup)

At falling of ports P00–P03, P54–P57 Valid when key input interrupt is selected

input logical level AND

External interrupt (falling valid)

Serial I/O1 receive 5

FFF516

FFF416 At completion of serial I/O1 data receive Valid only when serial I/O1 is selected

Serial I/O1 transmit 6

FFF316

FFF216 At completion of serial I/O1 transmit Valid only when serial I/O1 is selected

shift or transmit buffer is empty

Serial I/O2 receive 7

FFF116

FFF016 At completion of serial I/O2 data receive Valid only when serial I/O2 is selected

Serial I/O2 transmit 8

FFEF16

FFEE16 At completion of serial I/O2 transmit Valid only when serial I/O2 is selected

shift or transmit buffer is empty

Timer X

9

FFED16

FFEC16 At timer X underflow

Timer 1

10

FFEB16

FFEA16 At timer 1 underflow

Valid only when timer 1 interrupt is selected

Timer 2

11

FFE916

FFE816 At timer 2 underflow

Valid only when timer 2 interrupt is selected

Timer 3

12

FFE716

FFE616 At timer 3 underflow

Timer 4

13

FFE516

FFE416 At timer 4 underflow

CNTR0

14

FFE316

FFE216 At detection of either rising or falling External interrupt (active edge selectable)

edge of CNTR0 input

Timer Y

15

FFE116

FFE016 At timer Y underflow

CNTR1

At detection of either rising or falling External interrupt (active edge selectable)

edge of CNTR1 input

A-D conversion

16

FFDF16

FFDE16 At completion of A-D conversion

Valid when A-D conversion interrupt is se-

lected

BRK instruction

17

FFDD16

FFDC16 At BRK instruction execution

Non-maskable software interrupt

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

18

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