CXA2112R Ver la hoja de datos (PDF) - Sony Semiconductor

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componentes Descripción

Fabricante

CXA2112R

LCD Driver

Sony Semiconductor 

CXA2112R

Electrical Characteristics (See Electrical Characteristics Measurement Circuit.)

VDD = 5V, VCC = 15.5V, VSIGCEN = 7V, Ta = 25°C

No.

Item

1

VDD current

consumption

2

Vcc current

consumption

3 Invert amplifier gain

Symbol

Measurement

points

IDD

IVDD

ICC

AINV

IVCC1

IVCC2

VINV

VIN

4

Invert amplifier slew

rate

SRINV VINV

5

Invert amplifier output

band width

BWINV VINV

6

Output delay deviation

for inverse/non-inverse

TDIFF

7 SID gain

ASID

VINV

VSID

VSID_IN

8 SID output slew rate SRSID VSID

9

VCOM adjustable

range

10

Farst stage S/H slew

rate

VCOM VCOM

SRSH1

—

11 SH_OUT slew rate

SROUT

VOUT1 to

VOUT6

12

Output deviation

between channels ∗

DOUT

13

Dot clock input highest

frequency

fCLKH

14

Dot clock input lowest

frequency

fCLKL

VOUT1 to

VOUT6

fCLK

fCLK

15

Maximum output

voltage

VMAX

VOUT1 to

VOUT6

16

Minimum output

voltage

VMIN

VOUT1 to

VOUT6

Measurement contents

Min. Typ. Max. Unit

IDD = IVDD

22 32 42 mA

ICC = IVCC1 + IVCC2

30 41 52 mA

AINV = VINV (AC)/VIN

— 2.7 — times

Input a square wave from VIN so

that VINV output amplitude is

3.5Vp-p. Measure slew rate at 10 —

to 90% of output waveform rise or

fall. (for inverse or non-inverse)

Input 2.5V DC, 100mVp-p AC

from Pin 47 (VIDEO_IN) and

measure VINV. The frequency that —

is –3dB to 100kHz. (for inverse/

non-inverse)

Invert amplifier delay time

difference for inverse and non-

—

inverse.

700 — V/µs

90 — MHz

2 4 ns

ASID = VSID (AC)/VSID_IN

—

4 — times

Input invert pulse to Pin 44

(FRP), load capacity C7 = 47pF,

and apply DC input voltage to

VSID_IN so that VSID is 2.5V/11.5V.

—

Measure slew rate at 10 to 90%

of output waveform rise or fall.

30 — V/µs

VCOM output voltage when Pin

34 (VCOMOFST) is changed

from 0 to 10V.

Vsig – 2

or less

—

Vsig

V

First stage S/H slew rate on Block

Diagram.

—

700 — V/µs

Input a square wave from VIN so

that VOUT1 to VOUT6 output

amplitude is 3.5Vp-p. Measure

slew rate at 10 to 90% of output

—

waveform rise or fall. (load 270pF,

for inverse or non-inverse)

150 — V/µs

Apply DC voltage to VIN so that

VINV (SH_IN) is 6V.

—

3 10 mVp-p

Highest frequency for fCLK output

at correct timing.

100

115

MHz

Lowest frequency for fCLK output

at correct timing.

12 20 MHz

Maximum voltage at which

sample-and-hold output

(SH_OUT1 to SH_OUT6) can be

13

13.5

V

output.

Minimum voltage at which

sample-and-hold output

(SH_OUT1 to SH_OUT6) can be

output.

2 2.5 V

–9–

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