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KSZ9031RNX Datasheet PDF : 78 Pages
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KSZ9031RNX
3.17.3 LINK STATUS CHANGE DETECTION
If link status change detection is enabled, the KSZ9031RNX asserts its PME output pin low whenever there is a link
status change using the following MMD Address 2h registers bits and their enabled (1) or disabled (0) settings:
• MMD Address 2h, Register 10h, Bit [0]
• MMD Address 2h, Register 10h, Bit [1]
// For link-up detection
// For link-down detection
The PME output signal is available on either LED1/PME_N1 (Pin 17) or INT_N/PME_N2 (Pin 38), and is selected and
enabled using MMD Address 2h, Register 2h, Bits [8] and [10], respectively. Additionally, MMD Address 2h, Register
10h, Bits [15:14] defines the output functions for Pins 17 and 38.
The PME output is active low and requires a 1 kΩ pull-up to the VDDIO supply. When asserted, the PME output is
cleared by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status
change).
3.18 Typical Current/Power Consumption
Table 3-12, Table 3-13, Table 3-14, and Table 3-15 show the typical current consumption by the core (DVDDL, AVDDL,
AVDDL_PLL), transceiver (AVDDH), and digital I/O (DVDDH) supply pins, and the total typical power for the entire
KSZ9031RNX device for various nominal operating voltage combinations.
TABLE 3-12: TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (3.3V), DIGITAL I/O (3.3V)
Condition
1000BASE-T Link-Up (no traffic)
1000BASE-T Full-Duplex at
100% Utilization
100BASE-TX Link-Up (no traffic)
100BASE-TX Full-Duplex at
100% Utilization
10BASE-T Link-Up (no traffic)
10BASE-T Full-Duplex at
100% Utilization
Software Power-Down Mode
(Reg. 0h.11 = 1)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
210 mA
221 mA
3.3V Transceiver
(AVDDH)
67.4 mA
66.3 mA
63.6 mA
63.8 mA
28.7 mA
28.6 mA
7.1 mA
7.7 mA
15.9 mA
28.6 mA
1.0 mA
4.2 mA
3.3V Digital I/O
(DVDDH)
19.5 mA
41.5 mA
13.9 mA
17.2 mA
11.5 mA
13.7 mA
9.3 mA
Total
Chip Power
538 mW
621 mW
217 mW
228 mW
99 mW
149 mW
46 mW
TABLE 3-13: TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (3.3V), DIGITAL I/O (1.8V)
Condition
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
3.3V Transceiver
(AVDDH)
1000BASE-T Link-Up (no traffic)
1000BASE-T Full-Duplex at
100% Utilization
100BASE-TX Link-Up (no traffic)
100BASE-TX Full-Duplex at
100% Utilization
10BASE-T Link-Up (no traffic)
10BASE-T Full-Duplex at
100% Utilization
Software Power-Down Mode
(Reg. 0h.11 = 1)
210 mA
221 mA
63.6 mA
63.8 mA
7.1 mA
7.7 mA
1.0 mA
67.4 mA
66.3 mA
28.7 mA
28.6 mA
15.9 mA
28.6 mA
4.2 mA
1.8V Digital I/O
(DVDDH)
11.2 mA
23.6 mA
8.4 mA
9.8 mA
3.6 mA
5.6 mA
5.5 mA
Total
Chip Power
494 mW
526 mW
186 mW
189 mW
67 mW
114 mW
25 mW
2016 Microchip Technology Inc.
DS00002117C-page 29
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