Micrel, Inc.
KSZ9031RNX
Strapping Options
Pin Number Pin Name
35
PHYAD2
15
PHYAD1
17
PHYAD0
27
MODE3
28
MODE2
31
MODE1
32
MODE0
Type(3)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Function
The PHY address, PHYAD[2:0], is sampled and latched at power-up/reset and is
configurable to any value from 0 to 7. Each PHY address bit is configured as follows:
Pull-up = 1
Pull-down = 0
PHY Address Bits [4:3] are always set to ‘00’.
The MODE[3:0] strap-in pins are sampled and latched at power-up/reset as follows:
MODE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mode
Reserved – not used
Reserved – not used
Reserved – not used
Reserved – not used
NAND tree mode
Reserved – not used
Reserved – not used
Chip power-down mode
Reserved – not used
Reserved – not used
Reserved – not used
Reserved – not used
RGMII mode – advertise 1000Base-T full-duplex only
RGMII mode – advertise 1000Base-T full- and half-duplex only
RGMII mode – advertise all capabilities (10/100/1000 speed
half-/full-duplex), except 1000Base-T half-duplex
RGMII mode – advertise all capabilities (10/100/1000 speed
half-/full-duplex)
CLK125_EN is sampled and latched at power-up/reset and is defined as follows:
Pull-up = Enable 125MHz clock output
33
CLK125_EN
I/O
Pull-down = Disable 125MHz clock output
Pin 41 (CLK125_NDO) provides the 125MHz reference clock output option for use by
the MAC.
41
LED_MODE
Note:
3. I/O = Bi-directional.
LED_MODE is latched at power-up/reset and is defined as follows:
I/O
Pull-up = Single-LED mode
Pull-down = Tri-color dual-LED mode
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to an incorrect
configuration. In this case, Micrel recommends adding external pull-ups/pull-downs on the PHY strap-in pins to ensure the
PHY is configured to the correct pin strap-in mode.
May 14, 2015
14
Revision 2.2