IDT5P49V5901 Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT5P49V5901

PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5P49V5901

PROGRAMMABLE CLOCK GENERATOR

CLOCK SYNTHESIZER

IDT5P49V5901 Application Schematic

The following figure shows an example of IDT5P49V5901 application schematic. Input and output terminations shown are

intended as examples only and may not represent the exact user configuration. In this example, the device is operated at

VDDD, VDDA = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. A 12pF parallel

resonant 8MHz to 40MHz crystal is used in this example. Different crystal frequencies may be used. The C1 = C2 = 5pF are

recommended for frequency accuracy. If different crystal types are used, please consult IDT for recommendations. For

different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.

As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. IDT5P49V5901 provides separate power supplies to isolate any high

switching noise from coupling into the internal PLL.

In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device

side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should

be placed on the device side. The other components can be on the opposite side of the PCB.

Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the

devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate

noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supply

frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally,

good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all

devices.

The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and

functional tables in the datasheet to ensure the logic control inputs are properly set.

IDT® PROGRAMMABLE CLOCK GENERATOR

21

IDT5P49V5901

REV A 031014

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