IDT5P49V5901 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT5P49V5901 Datasheet PDF : 35 Pages
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IDT5P49V5901
PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Table 21: AC Timing Electrical Characteristics
(VDDO = 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol
Parameter
fIN 1 Input Frequency
Test Conditions
Input frequency limit (XIN)
Input frequency limit (REF)
Input frequency limit (CLKIN, CLKINB)
fOUT Output Frequency
Single ended clock output limit (LVCMOS)
Single ended reference clock output limit
(LVCMOS)
Differential clock output limit (LVPECL/
LVDS/HCSL)
fVCO
fPFD
fBW
t2
VCO Frequency
PFD Frequency
Loop Bandwidth
Input Duty Cycle
VCO operating frequency range
PFD operating frequency range
Input frequency = 25MHz
Duty Cycle
t3 Output Duty Cycle
Measured at VDD/2, all outputs except
Reference output
M(5eMaHszur-e1d5a0tMVHDzD)/2, Reference output
Measured at VDD/2, Reference output
(150.1MHz - 200MHz)
t4 2 Slew Rate, SLEW[1:0] = 00 Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF)
Slew Rate, SLEW[1:0] = 01 Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF)
Slew Rate, SLEW[1:0] = 10 Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF)
Slew Rate, SLEW[1:0] = 11 Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF)
t5 Rise Times
LVDS, 20% to 80%, single-ended
Fall Times
LVDS, 80% to 20%, single-ended
Rise Times
LVPECL, 20% to 80%, single-ended
Fall Times
LVPECL, 80% to 20%, single-ended
Min.
8
5
5
5
5
Typ.
Max.
40
200
350
200
150
Units
MHz
MHz
MHz
MHz
5
350
2800
0.81
100
0.08
0.5
45
55
45
55
MHz
MHz
MHz
%
%
40
60
%
35
70
%
1.83
V/ns
1.90
V/ns
1.96
V/ns
2.15
V/ns
300
ps
300
ps
400
ps
400
ps
IDT® PROGRAMMABLE CLOCK GENERATOR
16
IDT5P49V5901
REV A 031014
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