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RTL8111E-VL-CG

INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONS

Realtek Semiconductor 

RTL8111E

Datasheet

Figure 13. Reference Clock System Measurement Point and Loading

8.8.4. Auxiliary Signal Timing Parameters

Table 28. Auxiliary Signal Timing Parameters

Symbol

Parameter

Min

Max

Units

TPVPERL

TPERST-CLK

TPERST

TPERSTB-RTD

TFAIL*

Power Stable to PERSTB Inactive

REFCLK Stable before PERSTB Inactive

PERSTB Active Time

PERSTB Rising Time Duration

Power Level Invalid to PWRGD Inactive

100

-

ms

100

-

µs

100

-

µs

10

ms

-

500

ns

Note 1: TFAIL means 500 ns (maximum) from the power rail going out of specification (exceeding the specified tolerances

by more than 500 mV). Refer to PCI Local Bus Specification rev. 3.0 for further information. TFAIL can be disregarded

when implementation and timing of TFAIL will not affect any LAN functions.

Note 2: 3.3V means 3.3V main power. The ISOLATEB pin should follow the behavior of the 3.3V main power waveform.

Figure 14. Auxiliary Signal Timing

Integrated Gigabit Ethernet Controller for PCI Express

30

Track ID: JATR-2265-11 Rev. 1.1

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