RTL8111
Datasheet
Figure 10. REFCLK Vcross Range
7.7.4. Auxiliary Signal Timing Parameters
Symbol
TPVPERL
TPERST-CLK
TPERST
TFAIL
TWKRF
Table 20. Auxiliary Signal Timing Parameters
Parameter
Min
Max
Units
Power stable to PERSTB inactive
100
ms
REFCLK stable before PERSTB inactive
100
µs
PERSTB active time
100
µs
Power level invalid to PWRGD inactive
500
ns
LANWAKEB rise – fall time
100
ns
3.3 Vaux
3.3/12V
PERSTB
REFCLK
PCI-E Link
Inactive
Power Stable
Wakeup Event
Clock Stable
Clock not
Stable
T PVPERL
T PERST-CLK
Active
Inactive
T PERST
T FAIL
Figure 11. Auxiliary Signal Timing
Power Stable
Clock Stable
Active
Integrated Gigabit Ethernet Controller for PCI Express 22
Track ID: JATR-1076-21 Rev. 1.2