AD7533_04 Ver la hoja de datos (PDF) - Intersil
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AD7533_04 Datasheet PDF : 8 Pages
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AD7533
compatible operation. An external voltage or current
reference and an operational amplifier are all that is required
for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the
ladder leg currents between IOUT1 and IOUT2 buses which
must be held at ground potential. This configuration
maintains a constant current in each ladder leg independent
of the input code.
Converter errors are further reduced by using separate
metal interconnections between the major bits and the
outputs. Use of high threshold switches reduce offset
(leakage) errors to a negligible level.
The level shifter circuits are comprised of three inverters with
positive feedback from the output of the second to the first,
see Figure 1. This configuration results in TTL/CMOS
compatible operation over the full military temperature range.
With the ladder SPDT switches driven by the level shifter,
each switch is binarily weighted for an ON resistance
proportional to the respective ladder leg current. This
assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder
resistors and high accurate leg currents.
V+
TTL/
CMOS INPUT
13
4
6 TO LADDER
89
2
5
7
IOUT2 IOUT1
FIGURE 1. CMOS SWITCH
Typical Applications
DATA
INPUTS
±10V +15V
VREF
R1
MSB
LSB
15 14
4
16
AD7533 1
RFEEDBACK
OUT1
OUT2 CR1
11 3 2
GND
R2
-
6
+
VOUT
NOTES:
7. R1 and R2 used only if gain adjustment is required.
8. CR1 protects AD7533 against negative transients.
FIGURE 2. UNIPOLAR BINARY OPERATION
Unipolar Binary Operation - (10-Bit DAC)
The circuit configuration for operating the AD7533 in unipolar
mode is shown in Figure 2. With positive and negative VREF
values the circuit is capable of 2-Quadrant multiplication.
The “Digital Input Code/Analog Output Value” table for
unipolar mode is given in Table 1.
TABLE 1. UNlPOLAR BINARY CODE - AD7533
DIGITAL INPUT
MSB LSB
(NOTE 9)
NOMINAL ANALOG OUTPUT
1111111111
–VR E F 11----00---22----34-
1000000001
–VR E F 1--5--0--1-2--3--4-
1000000000
–VR
EF
1--5--0--1-2--2--4-
=
–V-----R----E----F-
2
0111111111
–VR E F 1--5--0--1-2--1--4-
0000000001
–VR E F 1----0--1-2----4-
0000000000
–VR
E
F
1----0--0-2----4-
=
0
NOTES:
9. VOUT as shown in Figure 2.
10. Nominal Full Scale for the circuit of Figure 2 is given by:
FS
=
–VR
E
F
11----00---22----34-
.
11. Nominal LSB magnitude for the circuit of Figure 2 is given by:
LSB
=
VR
EF
1----0--1-2----4-
.
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V ±1mV (Max) at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
4
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